Semiconductor device

• US 20060113577A1
• Filed: 09/20/2005
• Published: 06/01/2006
• Est. Priority Date: 09/28/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ohtani, Kinya
• Granted Patent: US 7,727,831 B2
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.

Claims

1. A semiconductor device having a field effect transistor, said field effect transistor comprises:

a semiconductor substrate;

a semiconductor layer formed on said semiconductor substrate;

a trench formed in said semiconductor layer;

a gate electrode provided within said trench via an gate insulating film intervening therebetween;

an insulating film provided on an upper portion of said gate electrode in the interior of said trench;

a source region provided on the side of said trench in an upper surface of said semiconductor layer;

a source electrode provided on upper portions of said insulating film and said source region;

a drain region provided under said trench; and

a drain electrode provided on a back surface of said semiconductor substrate,

wherein said insulating film provides an electrical insulation of said gate electrode from said source electrode,

wherein said semiconductor device comprises a cell portion and a terminal end provided in a periphery of said cell portion, and has said field effect transistor in said cell portion and has a trench in said terminal end, and

wherein a bottom surface of the trench provided on said terminal end is positioned to be lower than a bottom surface of the trench of said field effect transistor provided on said cell portion.

2. The semiconductor device according to claim 1, wherein a semiconductor element is provided in the trench provided on said terminal end.

3. The semiconductor device according to claim 2, wherein said semiconductor element is a diode.

4. The semiconductor device according to claim 2, wherein said semiconductor element is a field effect transistor.

5. The semiconductor device according to claim 1, wherein a depleted layer of said cell portion is blocked by disposing a bottom surface of the trench provided on said terminal end to be lower than a bottom surface of the trench of said field effect transistor provided on said cell portion.

6. The semiconductor device according to claim 1, wherein any portions of the upper surface of an insulating film provided in said cell portion and an insulating film provided in said terminal end are disposed at same level as or at lower level than the upper surface of said semiconductor layer.