Battery mounted integrated circuit device

• US 20060113652A1
• Filed: 04/02/2004
• Published: 06/01/2006
• Est. Priority Date: 04/04/2003
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shibano, Yasuyuki, Ishii, Hironori, Mino, Shinji E., Ugaji, Masaya
• Granted Patent: US 7,253,494 B2
• Time in Patent Office: Days
• US Class Current: 257/684
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01M 10/05 Accumulators with non-aqueous electrolyte H01M10/39 takes precedence
• CPC Class Codes: H01M 10/052 Li-accumulators
• CPC Class Codes: H01M 10/0561 the electrolyte being constituted of inorganic materials only
• CPC Class Codes: H01M 10/0565 Polymeric materials, e.g. gel-type or solid-type
• CPC Class Codes: H01M 10/4257 Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
• CPC Class Codes: H01M 50/117 Inorganic material
• CPC Class Codes: H01M 50/121 Organic material
• CPC Class Codes: H01M 50/124 having a layered structure
• CPC Class Codes: H01M 6/40 Printed batteries , e.g. thin film batteries
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

The present invention relates to a battery mounted integrated circuit device where an integrated circuit and a solid state battery are formed on the same substrate. In this battery mounted integrated circuit device, a first diffusion layer containing an N-type impurity is formed between a region of a semiconductor substrate where the solid state battery is mounted and a region of the semiconductor substrate where the integrated circuit is mounted, and a second diffusion layer containing an N-type impurity is formed below the region of the semiconductor substrate where the solid state battery is mounted, and overlaps with the first diffusion layer.

Claims

1. A battery mounted integrated circuit device, comprising:

(1) a semiconductor substrate;

(2) a solid state battery mounted on said semiconductor substrate;

(3) an integrated circuit mounted on said semiconductor substrate;

(4) a first diffusion layer, containing an N-type impurity, formed between a region of said semiconductor substrate where said solid state battery is mounted and an region of said semiconductor substrate where said integrated circuit is mounted; and

(5) a second diffusion layer, containing an N-type impurity, formed below said region of said semiconductor substrate where said solid state battery is mounted, and overlapping with said first diffusion layer,

said solid state battery comprising a positive electrode, a negative electrode, and a solid electrolyte disposed between said positive electrode and said negative electrode,

the concentration of said N-type impurity in said first diffusion layer is higher than the concentration of said N-type impurity in said second diffusion layer.

2. The battery mounted integrated circuit device in accordance with claim 1, wherein the concentration of said N-type impurity in said first diffusion layer is not less than 1×

10¹⁹ atoms/cm³.

3. The battery mounted integrated circuit device in accordance with claim 1, wherein the ratio of the concentration of said N-type impurity in said first diffusion layer to the concentration of said N-type impurity in said second diffusion layer is not more than 1×

10⁵.

4. The battery mounted integrated circuit device in accordance with claim 1, wherein said first diffusion layer and said second diffusion layer have a positive potential.

5. The battery mounted integrated circuit device in accordance with claim 4, wherein said positive potential is not less than a potential of said positive electrode with respect to said negative electrode.

6. The battery mounted integrated circuit device in accordance with claim 1, wherein said first diffusion layer surrounds said region where said solid state battery is mounted.

7. The battery mounted integrated circuit device in accordance with claim 1, further comprising a wiring layer for connecting said first diffusion layer with the outside.

8. The battery mounted integrated circuit device in accordance with claim 1, further comprising a potential controlling section for controlling a potential to be applied to said first diffusion layer and said second diffusion layer.