Semiconductor device

• US 20060113664A1
• Filed: 11/29/2005
• Published: 06/01/2006
• Est. Priority Date: 11/30/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Akiyama, Noboru, Uno, Tomoaki, Shiraishi, Masaki, Matsuura, Nobuyoshi
• Granted Patent: US 7,295,453 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: G05F 3/08 wherein the variable is dc
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/37124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40247 Connecting the strap to a bond pad of the item
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 : Parallel arrangements
• CPC Class Codes: H01L 2224/49431 : on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 2224/8485 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85375 : having an external coating, e.g. protective bond-through coating
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/4824 : Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4175 : for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41758 : for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS • FET for a high-side switch and a power MOS • FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS • FET for the high-side switch is formed by a p channel vertical MOS • FET, and the power MOS • FET for the low-side switch is formed by an n channel vertical MOS • FET. Thus, a semiconductor chip formed with the power MOS • FET for the high-side switch and a semiconductor chip formed with the power MOS • FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.

Claims

1. A semiconductor device comprising:

(a) a first chip mounting section having a first main surface and a second main surface placed on the opposite side thereof;

(b) a first external terminal which is disposed around the first chip mounting section and supplies a first power supply potential;

(c) a second external terminal which is disposed around the first chip mounting section and supplies a second power supply potential lower than the first power supply potential;

(d) output external terminals formed integrally with the first chip mounting section;

(e) a first semiconductor chip mounted over a first main surface of the first chip mounting section and having a source-to-drain path connected in series between the first external terminal and the output external terminals;

(f) a second semiconductor chip mounted over the first main surface of the first chip mounting section and having a source-to-drain path connected in series between the output external terminals and the second external terminal;

(g) wires which electrically connect electrodes formed in a main surface of the first semiconductor chip and the first external terminal to each other;

(h) wires which electrically connect electrodes formed in a main surface of the second semiconductor chip and the second external terminal to each other; and

(i) an encapsulator which seals the first semiconductor chip, the second semiconductor chip and the wires,

wherein a p channel first field effect transistor is formed in the first semiconductor chip,

wherein an n channel second field effect transistor is formed in the second semiconductor chip,

wherein the first field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a trench formed from the first surface of the semiconductor substrate to the second surface thereof;

a gate insulating film formed over an inner wall surface of the trench;

a gate electrode formed over the gate insulating film;

p type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode; and

n type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions,

wherein the second field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a trench formed from the first surface of the semiconductor substrate to the second surface thereof;

a gate insulating film formed over an inner wall surface of the trench;

a gate electrode formed over the gate insulating film;

n type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode;

p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and

a drain semiconductor region formed in the second surface, and

wherein the first semiconductor chip is disposed closer to the first external terminal than the center of the first chip mounting section.

2. The semiconductor device according to claim 1, wherein a control circuit that controls operations of the first field effect transistor and the second field effect transistor is accommodated within the encapsulator.

3. The semiconductor device according to claim 2, wherein the control circuit is formed in a third semiconductor chip separated from the first and second semiconductor chips, and the third semiconductor chip is mounted over a second chip mounting section separated from the first chip mounting section.

4. A semiconductor device comprising:

(a) a first chip mounting section having a first main surface and a second main surface disposed on the opposite side thereof;

(b) a first external terminal which is disposed around the first chip mounting section and supplies a first power supply potential;

(c) a second external terminal which is disposed around the first chip mounting section and supplies a second power supply potential lower than the first power supply potential;

(d) output external terminals formed integrally with the first chip mounting section;

(e) a first semiconductor chip mounted over a first main surface of the first chip mounting section and having a source-to-drain path connected in series between the first external terminal and the output external terminals;

(f) a second semiconductor chip mounted over the first main surface of the first chip mounting section and having a source-to-drain path connected in series between the output external terminals and the second external terminal;

(g) a first lead plate which electrically connects electrodes formed in a main surface of the first semiconductor chip and the first external terminal to each other;

(h) a second lead plate which electrically connects electrodes formed in a main surface of the second semiconductor chip and the second external terminal to each other; and

(i) an encapsulator which seals the first semiconductor chip and the second semiconductor chip,

wherein a p channel first field effect transistor is formed in the first semiconductor chip,

wherein an n channel second field effect transistor is formed in the second semiconductor chip,

wherein the first field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a trench formed from the first surface of the semiconductor substrate to the second surface thereof;

a gate insulating film formed over an inner wall surface of the trench;

a gate electrode formed over the gate insulating film;

p type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode; and

n type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions,

wherein the second field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a trench formed from the first surface of the semiconductor substrate to the second surface thereof;

a gate insulating film formed over an inner wall surface of the trench;

a gate electrode formed over the gate insulating film;

n type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode;

p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and

a drain semiconductor region formed in the second surface, and

wherein the first semiconductor chip is disposed closer to the first external terminal than a center of the first chip mounting section.

5. The semiconductor device according to claim 4, wherein one electrode of a capacitor is electrically connected to the first lead plate via a first junction layer, and the other electrode of the capacitor is electrically connected to the second lead plate via a second junction layer.

6. The semiconductor device according to claim 5, wherein the melting points of the first and second junction layers that bond the electrodes of the capacitor and the first and second lead plates are lower than the melting points of a third junction layer that bonds the first lead plate, the electrodes of the first semiconductor chip and the first external terminal, and a fourth junction layer that bonds the second lead plate, the electrodes of the second semiconductor chip and the second external terminal.

7. The semiconductor device according to claim 6, wherein the first and second junction layers comprise lead-tin solder, and the third and fourth junction layers comprise gold.

8. The semiconductor device according to claim 5, wherein the first lead plate and the second lead plate are partly exposed from the encapsulator, and the capacitor is mounted onto each of surfaces of the first and second lead plates exposed from the encapsulator.

9. The semiconductor device according to claim 5, wherein the first lead plate and the second lead plate are covered with the encapsulator over their entirety, and the capacitor is built in the encapsulator.

10. The semiconductor device according to claim 4, wherein depressions are defined in the surfaces of the first and second lead plates, which are in contact with the encapsulator.

11. A semiconductor device comprising:

(a) a first chip mounting section having a first main surface and a second main surface disposed on the opposite side thereof;

(b) a first external terminal which is disposed around the first chip mounting section and supplies a first power supply potential;

(c) a second external terminal which is disposed around the first chip mounting section and supplies a second power supply potential lower than the first power supply potential;

(d) output external terminals formed integrally with the first chip mounting section;

(e) a first semiconductor chip mounted over a first main surface of the first chip mounting section and having a source-to-drain path connected in series between the first external terminal and the output external terminals;

(f) a second semiconductor chip mounted over the first main surface of the first chip mounting section and having a source-to-drain path connected in series between the output external terminals and the second external terminal;

(g) wires which electrically connect electrodes formed in a main surface of the first semiconductor chip and the first external terminal to each other;

(h) wires which electrically connect electrodes formed in a main surface of the second semiconductor chip and the second external terminal to each other; and

(i) an encapsulator which seals the first semiconductor chip, the second semiconductor chip and the wires,

wherein an n channel first field effect transistor is formed in the first semiconductor chip,

wherein an n channel second field effect transistor is formed in the second semiconductor chip,

wherein the first field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a gate insulating film formed over the first surface of the semiconductor substrate;

a gate electrode formed over the gate insulating film;

n type semiconductor regions for a source and a drain, which are formed in the first surface and formed at both ends of the gate electrode; and

p type semiconductor regions for channel formation formed at a bottom face of the gate electrode and formed between the source and drain semiconductor regions,

wherein the second field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a trench formed from the first surface of the semiconductor substrate to the second surface thereof;

a gate insulating film formed over an inner wall surface of the trench;

a gate electrode formed over the gate insulating film;

n type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode;

p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and

a drain semiconductor region formed in the second surface, and

wherein the first semiconductor chip is disposed closer to the first external terminal than the center of the first chip mounting section.

12. The semiconductor device according to claim 11, wherein a control circuit that controls operations of the first field effect transistor and the second field effect transistor is accommodated within the encapsulator.

13. The semiconductor device according to claim 12, wherein the control circuit is formed in a third semiconductor chip separated from the first and second semiconductor chips, and the third semiconductor chip is mounted over a second chip mounting section separated from the first chip mounting section.

14. A semiconductor device comprising:

(a) a first chip mounting section having a first main surface and a second main surface disposed on the opposite side thereof;

(b) a first external terminal which is disposed around the first chip mounting section and supplies a first power supply potential;

(c) a second external terminal which is disposed around the first chip mounting section and supplies a second power supply potential lower than the first power supply potential;

(d) output external terminals formed integrally with the first chip mounting section;

(e) a first semiconductor chip mounted over a first main surface of the first chip mounting section and having a source-to-drain path connected in series between the first external terminal and the output external terminals;

(f) a second semiconductor chip mounted over the first main surface of the first chip mounting section and having a source-to-drain path connected in series between the output external terminals and the second external terminal;

(g) a first lead plate which electrically connects electrodes formed in a main surface of the first semiconductor chip and the first external terminal to each other;

(h) a second lead plate which electrically connects electrodes formed in a main surface of the second semiconductor chip and the second external terminal to each other; and

(i) an encapsulator which seals the first semiconductor chip and the second semiconductor chip, wherein an n channel first field effect transistor is formed in the first semiconductor chip,

wherein an n channel second field effect transistor is formed in the second semiconductor chip,

wherein the first field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a gate insulating film formed over the first surface of the semiconductor substrate;

a gate electrode formed over the gate insulating film;

n type semiconductor regions for a source and a drain, which are formed in the first surface and formed at both ends of the gate electrode; and

p type semiconductor regions for channel formation formed at a bottom face of the gate electrode and formed between the source and drain semiconductor regions,

wherein the second field effect transistor comprises;

a semiconductor substrate having a first surface and a second surface;

a trench formed from the first surface of the semiconductor substrate to the second surface thereof;

a gate insulating film formed over an inner wall surface of the trench;

a gate electrode formed over the gate insulating film;

n type semiconductor regions for a source, which are formed in the first surface and formed at both ends of the gate electrode;

p type semiconductor regions for channel formation formed at side faces of the gate electrode and formed between the source and drain semiconductor regions; and

a drain semiconductor region formed in the second surface, and

wherein the first semiconductor chip is disposed closer to the first external terminal than a center of the first chip mounting section.

15. The semiconductor device according to claim 14, wherein one electrode of a capacitor is electrically connected to the first lead plate via a first junction layer, and the other electrode of the capacitor is electrically connected to the second lead plate via a second junction layer.

16. The semiconductor device according to claim 15, wherein the melting points of the first and second junction layers that bond the electrodes of the capacitor and the first and second lead plates are lower than the melting points of a third junction layer that bonds the first lead plate, the electrodes of the first semiconductor chip and the first external terminal, and a fourth junction layer that bonds the second lead plate, the electrodes of the second semiconductor chip and the second external terminal.

17. The semiconductor device according to claim 16, wherein the first and second junction layers comprise lead-tin solder, and the third and fourth junction layers comprise gold.

18. The semiconductor device according to claim 15, wherein the first lead plate and the second lead plate are partly exposed from the encapsulator, and the capacitor is mounted onto each of surfaces of the first and second lead plates exposed from the encapsulator.

19. The semiconductor device according to claim 15, wherein the first lead plate and the second lead plate are covered with the encapsulator over their entirety, and the capacitor is built in the encapsulator.

20. The semiconductor device according to claim 14, wherein depressions are defined in the surfaces of the first and second lead plates, which are in contact with the encapsulator.