Automatic mode setting and power ramp compensator for system power on conditions

• US 20060114014A1
• Filed: 11/10/2005
• Published: 06/01/2006
• Est. Priority Date: 11/12/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: U-Nav Microelectronics (Qualcomm, Inc.)
• Inventors: Makarem, Rabih, Lam, Kwai-Kwong K., Leon, Christopher Rudolph
• Granted Patent: US 7,505,739 B2
• Time in Patent Office: Days
• US Class Current: 455/67.110
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01S 19/235 Calibration of receiver components
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/35 Constructional details or hardware or software details of the signal processing chain
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/36 simultaneously only, i.e. parallel type

Abstract

A GPS receiver with automatic mode-setting and power ramping circuitry is disclosed. AGPS receiver in accordance with the present invention comprises a first switch network, comprising a plurality of transistors, a first plurality of circuit components, coupled to the first switch network, wherein the switch network selects paths through the circuit components to generate a Power On Signal (POS) and ramp power to the GPS receiver, a plurality of test points, coupled to circuitry within the GPS receiver, wherein the test points are used to test intermediate stages of output of the GPS receiver, a second plurality of circuit components, each circuit component coupled to a corresponding test point in a respective manner, wherein the circuit components create outputs used in initialization of the GPS receiver, and a second switch network, coupled between the circuitry in the GPS receiver and the plurality of test points, for selectively switching the plurality of test points from being used to test intermediate stages of output of the GPS receiver and creating outputs used in initialization.

Claims

1. A mode-setting device for initializing a GPS receiver in a preferred state, comprising:

a plurality of test points, coupled to circuitry within the GPS receiver, wherein the test points are used to test intermediate stages of output of the GPS receiver;

a plurality of circuit components, each circuit component coupled to a corresponding test point in a respective manner, wherein the circuit components create outputs used in initialization of the GPS receiver; and

a switch network, coupled between the circuitry in the GPS receiver and the plurality of test points, for selectively switching the plurality of test points from being used to test intermediate stages of output of the GPS receiver and creating outputs used in initialization.

2. The mode-setting device of claim 1, wherein the circuit components are resistors.

3. The mode-setting device of claim 2, wherein the outputs used in initialization are logic level outputs.

4. The mode-setting device of claim 3, wherein the logic level outputs are used to select a mode of the GPS receiver during power up of the GPS receiver.

5. The mode-setting device of claim 4, wherein the selective switching of the test points is based on a presence of a Power On Signal (POS).

6. The mode-setting device of claim 5, wherein the selective switching of the test points is further based on a presence of an enable signal.

7. A Power On Signal (POS) generating device for ramping up power to a circuit during a power up state, comprising:

a switch network, comprising a plurality of transistors;

a plurality of capacitors, coupled to the switch network, wherein the switch network selectively charges each capacitor in a predetermined manner, wherein the predetermined manner is selected based on a quality of a power supply used to power up the circuit and POS signal is generated after the power supply has reached a desired voltage value.

8. The POS device of claim 7, wherein the device is used in a Global Positioning System (GPS) receiver.

9. The POS device of claim 8, wherein the POS device further generates a delayed POS signal.

10. The POS device of claim 9, wherein the device uses a fractional part of the power supply output and a base-emitter voltage to begin generation of the POS signal and the delayed POS signal.

11. The POS device of claim 10, further comprising a mode-setting device for initializing the GPS receiver.

12. The POS device of claim 11, wherein the mode-setting device comprises a plurality of test points, coupled to circuitry within the GPS receiver, wherein the test points are used to test intermediate stages of output of the GPS receiver;

a plurality of circuit components, each circuit component coupled to a corresponding test point in a respective manner, wherein the circuit components create outputs used in initialization of the GPS receiver; and

a second switch network, coupled between the circuitry in the GPS receiver and the plurality of test points, for selectively switching the plurality of test points from being used to test intermediate stages of output of the GPS receiver and creating outputs used in initialization.

13. The POS device of claim 12, wherein the POS device is resident on the GPS receiver chip.

14. A GPS receiver with initial mode-setting and power ramping circuitry, comprising:

a first switch network, comprising a plurality of transistors;

a first plurality of circuit components, coupled to the first switch network, wherein the switch network selects paths through the circuit components to generate a Power On Signal (POS) and ramp power to the GPS receiver;

a plurality of test points, coupled to circuitry within the GPS receiver, wherein the test points are used to test intermediate stages of output of the GPS receiver;

a second plurality of circuit components, each circuit component coupled to a corresponding test point in a respective manner, wherein the circuit components create outputs used in initialization of the GPS receiver; and

a second switch network, coupled between the circuitry in the GPS receiver and the plurality of test points, for selectively switching the plurality of test points from being used to test intermediate stages of output of the GPS receiver and creating outputs used in initialization.

15. The GPS receiver of claim 14, wherein the first plurality of circuit components is a plurality of capacitors.

16. The GPS receiver of claim 15, wherein the second plurality of circuit components is a plurality of resistors.