Charge-pump device with increased current output

• US 20060120157A1
• Filed: 11/09/2005
• Published: 06/08/2006
• Est. Priority Date: 11/11/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Vimercati, Daniele, Albano, Carmela
• Granted Patent: US 7,532,060 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

In a charge-pump device, a charge-pump circuit has an input, which is connected to a supply line and receives a supply voltage, and an output; in the charge-pump circuit a first elementary stage defines a first transfer node and a second transfer node that can be connected respectively to the input and to the output, and has at least one first phase input. In addition, in the first elementary stage a first switching element is arranged between the first transfer node and the second transfer node, has a control terminal receiving a control signal, and is closed during a charge-transfer interval; and first charge-storage means are connected between the control terminal and the first phase input. In the first elementary stage, a voltage-booster stage has an input connected to the first phase input of the first elementary stage, and an output connected to the first charge-storage means and supplies a boosted phase signal; in particular, the voltage-booster stage is operative during the charge-transfer interval.

Claims

1. A charge-pump device comprising a charge-pump circuit having an input connected to a supply line and receiving a supply voltage, and an output;

said charge-pump circuit having at least one first elementary stage defining a first transfer node and a second transfer node that can be connected respectively to said input and to said output, and having at least a first phase input;

said first elementary stage further comprising;

a first switching element, arranged between said first transfer node and said second transfer node and having a control terminal receiving a control signal, said first switching element being closed during a charge-transfer interval; and

first charge-storage means connected between said control terminal and said first phase input;

wherein said first elementary stage further comprises a voltage-booster stage having an input connected to said first phase input of said first elementary stage, and an output, which is connected to said first charge-storage means and supplies a boosted phase signal;

said voltage-booster stage being configured to be operative during said charge-transfer interval.

2. The device according to claim 1, wherein said first switching element is a MOS transistor having a first conduction terminal connected to said first transfer node, a second conduction terminal connected to said second transfer node, and a gate terminal defining said control terminal.

3. The device according to claim 1, wherein said first phase input receives a first phase signal, and wherein said first elementary stage has a second phase input receiving a second phase signal and further comprises:

second charge-storage means connected between said second transfer node and said second phase input; and

a second switching element having a first terminal connected to said first transfer node, a second terminal connected to said control terminal of said first switching element, and a control terminal connected to said second transfer node.

4. The device according to claim 1, further comprising a phase-generator stage having an input receiving a clock signal and a plurality of outputs supplying a plurality of phase signals;

said phase signals being temporally offset with respect to said clock signal, and switching repeatedly between a first level and a second level; and

wherein said charge-pump circuit comprises at least one second elementary stage, which is cascaded to said first elementary stage and has an own first phase input;

said first and second elementary stages having an own second phase input;

said first and second elementary stages receiving a respective first phase signal on a respective first phase input, and a respective second phase signal on a respective second phase input.

5. The device according to claim 4, wherein the second phase signals received by said first and second elementary stages have simultaneous switching with respect to said clock signal.

6. The device according to claim 4, wherein each second phase signal switches after a given delay with respect to the respective first phase signal.

7. The device according to claim 1, wherein said voltage-booster stage comprises:

a first inverter, having a first input connected to said first phase input and receiving a first phase signal, a second input connected to a boosted line, and an output connected to said first charge-storage means; and

voltage-modifying means configured to vary the voltage of said boosted line.

8. The device according to claim 7, wherein said first phase signal switches between a first voltage level and a second voltage level, and wherein said voltage-modifying means are controlled by said phase signal.

9. The device according to claim 8, wherein said voltage-modifying means generate at output a voltage equal to twice said supply voltage when said first phase signal assumes said first voltage level, and generate at output a voltage equal to said supply voltage when said phase signal assumes said second voltage level.

10. The device according to claim 7, wherein said voltage-modifying means comprise:

a first logic inverter having a first input receiving said phase signal, a second input receiving said supply voltage, and an output;

third charge-storage means having a first terminal connected to the output of said first logic inverter, and a second terminal connected to said boosted line; and

a unidirectional switching stage connected between said supply line and said boosted line.

11. The device according to claim 10, wherein said unidirectional switching stage comprises:

a second inverter having a first input receiving said first phase signal, a second input connected to said boosted line, and an output; and

a third switching element having a first terminal connected to said supply line, a second terminal connected to said boosted line, and a control terminal connected to the output of said second inverter.

12. A memory device comprising an array of memory cells, and a charge-pump device having an output connected to a current-conduction terminal of said memory cells, wherein said charge-pump device is constructed according to claim 1.

13. A portable apparatus comprising a memory device according to claim 12;

wherein said portable apparatus is a mobile phone apparatus.

14. A method of operation of a charge-pump device, comprising a charge-pump circuit receiving a supply voltage and supplying an output voltage, and having at least one first elementary stage including a first switching element provided with an input terminal, an output terminal and a control terminal, and first charge-storage means connected to said control terminal;

said method comprising supplying a first phase signal to said first charge-storage means, said first phase signal switching between a first value and a second value such as to cause switching of said first switching element between a conduction state and an inhibition state; and

boosting said first phase signal up to a boosted value higher than said supply voltage when said first switching element is in said conduction state.

15. The method according to claim 14, wherein said boosted value is theoretically equal to at least twice said supply voltage.

16. The method according to claim 14, for a charge-pump device comprising at least one second elementary stage cascaded to said first elementary stage and including an own first switching element provided with own input terminal, output terminal, and control terminal, and own first charge-storage means connected to said own control terminal and receiving a first phase signal;

said first and second elementary stages comprising second charge-pump means connected to the output terminal of the respective first switching element;

said method further comprising supplying a respective second phase signal to said second charge-pump means of said first and second elementary stages;

said second phase signals of said first and second elementary stages switching between a respective first level and second level, and having approximately simultaneous level switching with respect to a clock signal.

17. The method according to claim 16, wherein said second phase signals switch with a given delay with respect to a respective first phase signal.