Condensed galois field computing system

• US 20060123325A1
• Filed: 11/22/2004
• Published: 06/08/2006
• Est. Priority Date: 11/22/2004
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Wilson, James, Stein, Yosef, Kablotsky, Joshua
• Granted Patent: US 7,512,647 B2
• Time in Patent Office: Days
• US Class Current: 714/781
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/158 Finite field arithmetic processing

Abstract

A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

Claims

1. A condensed Galois field computing system comprising:

a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and

a Galois field linear transformer circuit for applying an irreducible polynomial of power n to said product including a partial result generator responsive to terms of power n and greater in said product for providing a folded partial result and a Galois field adder for combining said folded partial result and the terms less than power n in the product to obtain Galois field transform of power n of said product.

2. The condensed Galois field computing system of claim 1 in which said partial result generator includes a look-up table.

3. The condensed Galois field computing system of claim 2 in which said look-up table includes the folded partial results for the combinations of n or greater.

4. The condensed Galois field computing system of claim 2 in which said look-up table includes an address generator for said selecting one of the folded partial results tables.

5. The condensed Galois field computing system of claim 4 in which said address generator provides statically independent address access.

6. The condensed Galois field computing system of claim 1 in which said Galois field adder includes a three input adder.

7. The condensed Galois field computing system of claim 6 in which said third input to said three input adder is a zero and said Galois field computing system operates as a Galois field multiplier.

8. The condensed Galois field computing system of claim 6 in which said third input to said three input adder is the Galois field adder output fed back and said Galois field computing system operates as a multiplier-accumulator.

9. The condensed Galois field computing system of claim 6 in which the Galois field adder output is fed back to said multiplier circuit with one of said first and second polynomials and the other of said polynomials is the third input to said Galois field adder and said Galois field computing system operates as a multiplier-adder.

10. The condensed Galois field computing system of claim 1 in which the Galois field adder includes an exclusive OR circuit.

11. The condensed Galois field computing system of claim 4 in which said address generator includes an OR circuit for combining said terms of n and greater and said value of base address to generate the look-up table address.

12. The condensed Galois field computing system of claim 2 in which said look-up table includes at least one folded partial results table

13. A condensed Galois field multiplier system comprising:

a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and

a Galois field linear transformer circuit for applying an irreducible polynomial of power n to said product including a partial result generator responsive to terms of power n and greater in said product for providing a folded partial result and a Galois field adder for combining said folded partial results and the terms less than power n in the product to perform a Galois field multiply operation.

14. A condensed Galois field multiply-accumulate system comprising:

a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and

a Galois field linear transformer circuit for applying an irreducible polynomial of power n to said product including a partial result generator responsive to terms of power n and greater in said product for providing a folded partial result and a Galois field adder for combining said folded partial results, the terms less than power n in the product and the output of the Galois field adder fed back to perform a Galois field multiply-accumulate operation.

15. A condensed Galois field multiplier-adder system comprising:

a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and

a Galois field linear transformer circuit for applying an irreducible polynomial of power n to said product including a partial result generator responsive to terms of power n and greater in said product for providing a folded partial result and a Galois field adder whose output is fed back to said multiplier circuit with one of said first and second polynomials and the other of said polynomials is a third input to said Galois field adder along with said folded partial results and the terms less than power n in the product to perform a Galois field multiply-add operation.