Method for fabricating an array substrate for IPS mode liquid crystal display device

• US 20060132693A1
• Filed: 01/30/2006
• Published: 06/22/2006
• Est. Priority Date: 12/24/2001
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kim, Ik-Soo, Chae, Gee-Sung
• Granted Patent: US 7,480,024 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

An array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device includes a pixel electrode having an extension portion, a vertical portion and a horizontal portion, the extension portion being extended from the drain electrode to the pixel region, the vertical portion being vertically extended from the extension portion and the horizontal portion being over the common line and being connected to the vertical portion. The device includes a common electrode having a plurality of vertical portions and a horizontal portion, the plurality of the vertical portions being vertically extended from the common line and arranged in an alternating pattern with the vertical portion of the pixel electrode, the horizontal portion connecting the plurality of the vertical portions into one. An auxiliary line is over the horizontal portion of the pixel electrode and being overlapped with the common line.

Claims

1-19. -19. (canceled)

20. A method for fabricating an array substrate for in-plane switching mode liquid crystal display device, comprising:

forming a plurality of gate lines, a gate electrode, a plurality of common lines, a common electrode and a dummy line on a substrate, the dummy line being formed in a non-display area;

forming a first insulating layer over the substrate;

forming a semiconductor layer on the first insulating layer;

forming a plurality of data lines, source and drain electrodes and a pixel electrode on the semiconductor layer;

forming a second insulating layer over the substrate; and

forming an auxiliary line on the second insulating layer, the auxiliary line being overlapped with the common line and one end of the auxiliary line communicating with the dummy line.

21. The method according to claim 20, wherein the gate line, the common line and the dummy line are formed using the same material on a same layer.

22. The method according to claim 20, wherein the gate line, the common line and the dummy line are formed of one of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), molybdenum (Mo), copper (Cu) and chromium (Cr).

23. The method according to claim 20, wherein the auxiliary line is formed of one of Indium-Tin-Oxide (ITO) and Indium Zinc Oxide (IZO).

24. The method according to claim 20, wherein the first insulating layer is formed of one of silicon nitride (SiNx) and silicon oxide (SiO₂).

25. The method according to claim 20, wherein the second insulating layer is formed of one of silicon nitride (SiNx) and silicon oxide (SiO₂).

26. The method according to claim 20, wherein the common line and the pixel electrode to form a first storage capacitor.

27. The method according to claim 20, wherein the pixel electrode and the auxiliary line to form a second storage capacitor.