Method for making a neo-layer comprising embedded discrete components

• US 20060134835A1
• Filed: 02/14/2006
• Published: 06/22/2006
• Est. Priority Date: 11/06/2002
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: He, Sambo
• Granted Patent: US 7,198,965 B2
• Time in Patent Office: Days
• US Class Current: 438/124
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/0268 : for electrical inspection or testing
• CPC Class Codes: H05K 1/187 : the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
• CPC Class Codes: H05K 2201/0919 : Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes shielding provided by an inner layer of PCB H05K2201/0723
• CPC Class Codes: H05K 2203/0152 : Temporary metallic carrier, e.g. for transferring material affixing a prefabricated conductor pattern formed by electroplating or electroforming on a metallic carrier H05K3/205
• CPC Class Codes: H05K 2203/061 : of previously made multilayered subassemblies laminating only or mainly similar single-sided circuit boards H05K3/4617; laminating only or mainly similar double-sided circuit boards H05K3/462
• CPC Class Codes: H05K 2203/162 : Testing a finished product, e.g. heat cycle testing of solder joints patterns for electrical inspection or testing H05K1/0268
• CPC Class Codes: H05K 3/108 : by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/20 : by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or wire bonded components are attached thereto. An under-bump metal process step is disclosed and provides for solder attachment at desired contact pad locations. The layer is encapsulated in a potting material and thinned to provide a thin, stackable layer. When assembled into a stack of layers, the electrically conductive traces terminating at the edge of the layer can be electrically connected by means of electroplating using a T-connect.

Claims

1. A method for making a stackable layer comprising the steps of:

providing a sacrificial substrate having a first surface and a second surface,

defining a first dielectric layer on said first surface,

defining a plurality of electrically conductive traces on said first dielectric layer,

defining a second dielectric layer upon said first dielectric layer whereby said electrically conductive traces are encapsulated therein,

removing predetermined portions of said second dielectric layer to expose portions of said electrically conductive traces to define a plurality of contact pads,

electrically connecting at least one discrete electrical component to at least one of said contact pads,

encapsulating said second dielectric layer and said at least one discrete electrical component in a potting material,

removing said sacrificial layer to define a component surface and a test surface, and,

defining one or more vias in said test surface to define a test contact pad.

2. The method of claim 1 where said substrate is an aluminum material.

3. The method of claim 1 where said substrate is removed by etching.

4. The method of claim 1 where said dielectric is a polyimide material.

5. The method of claim 1 further comprising the step of testing said stackable layer.

6. The method of claim 1 wherein said at least one discrete electrical component is electrically connected by means of a wire bond.

7. The method of claim 1 further comprised of removing a predetermined portion said potting material.

8. A method for making a stackable layer comprising the steps of:

providing a sacrificial substrate having a first surface and a second surface,

defining a first dielectric layer on said first surface,

defining a plurality of electrically conductive traces on said first dielectric layer,

defining a second dielectric layer upon said first dielectric layer whereby said traces are encapsulated therein,

removing predetermined portions of said second dielectric layer to define a plurality of contact pads,

providing an under-bump metal on at least one of said contact pads to define an under-bump metal contact pad

electrically connecting at least one discrete electrical component to at least one of said under-bump metal contact pads by means of a solder connection,

encapsulating said at least one discrete electrical component in a potting material,

removing said sacrificial layer to define a component surface and a test surface, and,

defining one or more vias in said test surface to define a test contact pad.

9. The method of claim 8 wherein said at least one discrete electrical component is a thick film surface mount component.

10. The method of claim 8 wherein said at least one discrete electrical component is a thin film surface mount component.

11. The method of claim 8 where said substrate is an aluminum material.

12. The method of claim 8 where said substrate is removed by etching.

13. The method of claim 8 where said dielectric is a polyimide material.

14. The method of claim 8 further comprising the step of testing said stackable layer.

15. The method of claim 8 wherein said at least one discrete electrical component is electrically connected by means of a wire bond.

16. The method of claim 8 further comprised of removing a predetermined portion said potting material.