Silicon carbide on diamond substrates and related devices and methods

• US 20060138455A1
• Filed: 02/06/2006
• Published: 06/29/2006
• Est. Priority Date: 01/22/2004
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: Adam William Saxler
• Inventors: Saxler, Adam William
• Granted Patent: US 7,579,626 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence

Abstract

A high power, wide-bandgap device is disclosed that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density. The device includes a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide, a single crystal silicon carbide layer on the diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond, and a Group III nitride heterostructure on the single crystal silicon carbide layer for providing device characteristics.

Claims

1. A high power, wide-bandgap device that exhibits reduced junction temperature and higher power density during operation and improved reliability at a rated power density, said device comprising:

a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide;

a single crystal silicon carbide layer on said diamond substrate for providing a supporting crystal lattice match for wide-bandgap material structures that is better than the crystal lattice match of diamond; and

a Group III nitride heterostructure on said single crystal silicon carbide layer for providing device characteristics.

2. A device according to claim 1 comprising a polycrystalline diamond substrate.

3. A device according to claim 1 wherein said silicon carbide layer is semi-insulating.

4. A device according to claim 1 further comprising a Group III nitride buffer layer on said silicon carbide layer for providing a crystal and electronic transition between said heterostructure and said silicon carbide layer.

5. A device according to claim 4 wherein said buffer layer comprises aluminum nitride.

6. A device according to claim 1 wherein said silicon carbide has a polytype selected from the 3C, 4H, 6H and 15R polytypes of silicon carbide.

7. A device according to claim 1 further comprising respective ohmic contacts to said heterostructure.

8. A device according to claim 1 packaged in a high-thermal conductivity material.

9. A packaged device according to claim 8 wherein said high-thermal conductivity material comprises diamond.

10. A wide-bandgap high electron mobility transistor (HEMT) comprising:

a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide;

a semi-insulating single crystal silicon carbide layer on said diamond substrate for providing a favorable crystal growth surface for Group III nitride epilayers;

a buffer layer on said silicon carbide layer for providing an enhanced crystal transition between silicon carbide and a Group III nitride;

a first epitaxial layer of a first Group III nitride on said buffer layer;

a second epitaxial layer of a different Group III nitride on said first epitaxial layer for forming a heterojunction with said first epilayer, and with said Group III nitride of said second epilayer having a wider bandgap than said first Group III nitride of said first epilayer for generating a two-dimensional electron gas in the first epilayer at the interface of said first and second epilayers; and

respective source, gate, and drain contacts to said second epitaxial Group III nitride layer for providing a flow of electrons between the source and drain that is controlled by a voltage applied to the gate.

11. A HEMT according to claim 10 wherein said first epitaxial layer comprises gallium nitride and said second epitaxial layer comprises aluminum gallium nitride.

12. A HEMT according to claim 11 wherein said gallium nitride layer is undoped and said aluminum gallium nitride layer is n-doped.

13. A HEMT according to claim 10 wherein said first epitaxial layer comprises gallium nitride and said second epitaxial layer comprises a doped layer of aluminum gallium nitride and an undoped layer of aluminum gallium nitride, with said undoped aluminum gallium nitride layer adjacent said undoped gallium nitride layer.

14. A HEMT according to claim 10 wherein said first epitaxial layer comprises gallium nitride and said second epitaxial layer comprises a layer of aluminum gallium nitride and an undoped layer of aluminum nitride, with said undoped aluminum nitride layer adjacent said undoped gallium nitride layer.

15. A HEMT according to claim 10 packaged in a high thermal-conductivity material.

16. A HEMT according to claim 10 and further comprising a mechanical substrate for said diamond substrate for providing additional mechanical support to said HEMT.

17. A HEMT according to claim 10 wherein said diamond substrate is formed of at least two discrete diamond layers that differ from one another in their properties.

18. A HEMT according to claim 10 wherein said silicon carbide layer is bonded to said diamond substrate.

19. A device according to claim 10 packaged in a high-thermal conductivity material.

20. A packaged device according to claim 15 wherein said high-thermal conductivity material comprises diamond.

21. A wide-bandgap high electron mobility transistor (HEMT) comprising:

a diamond substrate for providing a heat sink with a thermal conductivity greater than silicon carbide;

a semi insulating single crystal silicon carbide layer on said diamond substrate for providing a favorable crystal growth surface for Group III nitride epilayers;

a Group III nitride buffer layer on said silicon carbide substrate;

an epitaxial layer of gallium nitride on said buffer layer;

an epitaxial layer of aluminum gallium nitride on said gallium nitride epitaxial layer for forming a heterojunction with said gallium nitride epilayer with said aluminum gallium nitride having a wider bandgap than said gallium nitride epitaxial layer for generating a two-dimensional electron gas in said gallium nitride epilayer at the interface of said gallium nitride and aluminum gallium nitride epilayers; and

respective source, gate, and drain contacts to the aluminum gallium nitride layer for providing a flow of electrons between the source and drain that is controlled by a voltage applied to the gate.

22. A HEMT according to claim 21 wherein said gallium nitride layer is undoped and said aluminum gallium nitride layer is n-doped.

23. A HEMT according to claim 21 wherein said buffer layer comprises aluminum nitride.

24. A HEMT according to claim 21 wherein said aluminum gallium nitride layer is formed of a doped layer and an undoped layer, with the undoped aluminum gallium nitride layer adjacent said undoped gallium nitride layer and said ohmic contacts being to said doped layer.

25. A HEMT according to claim 21 wherein said aluminum gallium nitride layer is formed of a doped layer between two undoped layers with one of said undoped layers being adjacent said undoped gallium nitride layer and the other of said undoped layers being in contact with said respective ohmic contacts.

26. A HEMT according to claim 21 and further comprising a passivation layer above said heterojunction.

27. A HEMT according to claim 21 packaged in a high-thermal conductivity material.

28. A packaged device according to claim 27 wherein said high-thermal conductivity material comprises diamond.

29. A wafer precursor for semiconductor devices comprising:

a substrate of single crystal silicon carbide that is at least two inches in diameter; and

a layer of diamond on a first face of said silicon carbide substrate;

wherein the opposite face of said silicon carbide substrate is prepared for Group III nitride epitaxial growth thereon.

30. A wafer precursor according to claim 29 comprising a Group III nitride active structure on said prepared opposite face.

31. A wafer precursor according to claim 29 wherein said silicon carbide substrate is at least three inches in diameter.

32. A wafer precursor according to claim 29 wherein said silicon carbide substrate is at least 100 mm in diameter.

33. A wafer precursor according to claim 30 wherein said Group III nitride active structure includes at least one heterostructure.

34. A wafer precursor according to claim 33 comprising a buffer layer on said silicon carbide substrate and between said substrate and said heterostructure.

35. A wafer precursor according to claim 29 wherein said silicon carbide has a polytype selected from the group consisting of the 3C, 4H, 6H and 15R polytypes of silicon carbide.

36. A wafer precursor according to claim 29 comprising a plurality of individual active structures on said prepared face of said silicon carbide substrate.

37. A semiconductor laser comprising:

a diamond substrate;

a single crystal silicon carbide layer on said diamond substrate;

at least a first cladding layer on said silicon carbide layer;

a Group III nitride active portion on said at least one cladding layer; and

at least a second cladding layer on said active portion.

38. A semiconductor laser according to claim 37 further comprising a buffer layer between said silicon carbide layer and said first cladding layer.

39. A semiconductor laser according to claim 37 comprising a polycrystalline diamond substrate.

40. A semiconductor laser according to claim 37 wherein said silicon carbide has a polytype selected from the 3C, 4H, 6H and 15R polytypes of silicon carbide.