Method for verifying smart battery failures by measuring input charging voltage and associated systems
First Claim
1. A method for verifying failures in a battery for an information handling system, comprising:
- monitoring a battery for a charging current, the battery including a discharge transistor (D-FET) coupled between an input for the battery and a cell pack for the battery;
when a charging current above a desired current threshold level is detected when the battery is not in charge mode, turning off the D-FET, if it is on, and measuring an input terminal voltage level for the battery after; and
utilizing the input terminal voltage level measurement to facilitate a determination of whether or not the detected charging current represents a charging failure.
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Abstract
A method and associated system are disclosed for verifying charging failures for smart batteries by measuring input charging voltage and associated systems. In one embodiment, a determination is made whether or not a charging current is indicative of a battery failure by utilizing an analog-to-digital (A/D) port to measure the input charging voltage. As long as the measured input charging voltage is below the cell pack voltage or some set voltage value, whichever is higher, the BMU considers a charging current detection to be a false failure indication. If the measured charging voltage is above the cell pack voltage or a set voltage value, whichever is lower, the BMU considers the charging current detection to be a positive failure indication. The BMU can then disable the battery or implement other verification steps before disabling the battery, as desired.
53 Citations
20 Claims
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1. A method for verifying failures in a battery for an information handling system, comprising:
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monitoring a battery for a charging current, the battery including a discharge transistor (D-FET) coupled between an input for the battery and a cell pack for the battery;
when a charging current above a desired current threshold level is detected when the battery is not in charge mode, turning off the D-FET, if it is on, and measuring an input terminal voltage level for the battery after; and
utilizing the input terminal voltage level measurement to facilitate a determination of whether or not the detected charging current represents a charging failure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A battery utilizing input charging voltages to verify charging failures, comprising:
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positive and negative input terminals;
a cell pack coupled to drive the positive and negative input terminals;
a battery management unit (BMU), including a microcontroller and analog front end (AFE) circuitry;
a charge transistor (C-FET) coupled between the positive input terminal and the cell pack and coupled to be controlled by the BMU;
a discharge transistor (D-FET) coupled between the positive input terminal and the cell pack and coupled to be controlled by the BMU;
a current sense resistor coupled between the negative input terminal and the cell pack;
a current input analog-to-digital converter (ADC) coupled to the current sense resistor; and
a voltage input analog-to-digital converter (ADC) coupled to the positive and negative input terminals;
wherein the BMU is configured to utilize charging voltage values from the voltage input ADC to verify charging failures. - View Dependent Claims (13, 14, 15, 16)
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17. An information handling system configured to be powered by a battery or an alternating current to direct current (AC/DC) converter, comprising:
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an alternating current to direct current (AC/DC) converter;
a load coupled to the AC/DC converter, the load representing powered circuitry for an information handling system;
a charger coupled to the AC/DC converter;
a battery coupled to the charger and to the load, the battery comprising;
positive and negative input terminals;
a cell pack coupled to drive the positive and negative input terminals;
a battery management unit (BMU), including a microcontroller and analog front end (AFE) circuitry;
a charge transistor coupled (C-FET_between the positive input terminal and the cell pack and coupled to be controlled by the BMU;
a discharge transistor coupled (D-FET) between the positive input terminal and the cell pack and coupled to be controlled by the BMU;
a current sense resistor coupled between the negative input terminal and the cell pack;
a current input analog-to-digital converter (ADC) coupled to the resistor; and
a voltage input analog-to-digital converter (ADC) coupled to the positive and negative input terminals;
wherein the BMU is configured to utilize charging voltage values from the voltage input ADC to verify charging failures. - View Dependent Claims (18, 19, 20)
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Specification