Technique for increased exposure range in image sensors

• US 20060139470A1
• Filed: 12/29/2004
• Published: 06/29/2006
• Est. Priority Date: 12/29/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McGowan, Steven B.
• Granted Patent: US 8,081,234 B2
• Time in Patent Office: Days
• US Class Current: 348/294
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An apparatus comprising an image sensor and a control logic circuit. The image sensor includes at least a first pixel array and a second pixel array, wherein at least some of the pixels of the first pixel array are interspersed over an image sensing area with pixels of the second pixel array. The control logic circuit is operable to control durations of exposure of the first pixel array and the second pixel array independently.

Claims

1. An apparatus comprising:

an image sensor including at least a first pixel array and a second pixel array, wherein at least some of the pixels of the first pixel array are interspersed over an image sensing area with pixels of the second pixel array; and

a control logic circuit to control exposure of the first pixel array and the second pixel array.

2. The apparatus of claim 1, wherein pixels of the first pixel array and pixels of the second pixel array are interspersed on the image sensor in an alternating arrangement.

3. The apparatus of claim 1, wherein pixels of the first pixel array and pixels of the second pixel array are interspersed on the image sensor in a checkerboard arrangement.

4. The apparatus of claim 1, wherein the control logic circuit is operable to determine the commencement of the exposure of the second pixel array, or the duration of the exposure of the second pixel array, or both, in relation to the exposure of the first pixel array.

5. The apparatus of claim 1, wherein the control logic circuit includes programmable logic to independently determine the exposure of the first and second pixel arrays.

6. The apparatus of claim 5, wherein the control logic determines the exposure of the first and second pixel arrays based on a desired luminance of at least some pixels.

7. The apparatus of claim 1, wherein the control logic circuit is operable to place a delay between the commencement of the exposure of the first pixel array and the commencement of the exposure of the second pixel array.

8. The apparatus of claim 7, wherein the exposure of the second pixel array is centered within the exposure of the first pixel array.

9. The apparatus of claim 1 further including a flash control circuit coupled to the control logic circuit, wherein the commencement of the exposure, or the duration of the exposure, or both, of at least the first pixel array are determined in relation to an illumination of a flash.

10. The apparatus of claim 1, wherein at least one pixel of the first or second pixel arrays is a color pixel comprised of a plurality of monochrome pixels.

11. The apparatus of claim 1, further including a memory circuit to store image information obtained from the first pixel array and image information obtained from the second pixel array.

12. The apparatus of claim 1, wherein the at least a first pixel array and a second pixel array includes three or more pixel arrays, wherein the pixels of at least a third pixel array are interspersed with the pixels of the first and second pixel arrays, wherein the third pixel array is operable to have an exposure different from the first or second pixel arrays, and wherein the control logic circuit is operable to determine the exposure of the first, second and third pixel arrays.

13. The apparatus of claim 12, wherein the control logic is operable to expose the first pixel array to an image for a longer time than the second pixel array, and to expose the third pixel array to an image for a shorter time than the second pixel array.

30. The method of claim 20, the method of claim 1, wherein providing storage for image information includes providing storage for combined image information obtained from the first pixel array and the second pixel array.

14. A system comprising:

a memory circuit, the memory circuit including a removably coupled flash memory;

an image sensor to provide image information to the memory circuit, the image sensor including at least a first pixel array and a second pixel array, wherein at least some of the pixels of the first pixel array are interspersed with pixels of the second pixel array, and wherein the first pixel array can be exposed to an image differently than the second pixel array can be exposed to the image; and

a microprocessor coupled to the memory circuit and the image sensor to provide control of the exposure of the first pixel array and the second pixel array to the image.

15. The system of claim 14, wherein the microprocessor is operable to combine image information obtained from the at least first pixel array and second pixel array.

16. The system of claim 15, wherein combining image information includes replacing empty pixels, or saturated pixels, or both, with image information from an adjacent pixel location where the corresponding adjacent pixel is not empty or saturated.

17. The system of claim 14 further including a flash control circuit coupled to the microprocessor, wherein the microprocessor determines an exposure of at least the first pixel array in relation to an illumination of a flash.

18. The system of claim 14, wherein pixels of the first pixel array and pixels of the second pixel array are interspersed on the image sensor in a checkerboard arrangement.

19. The system of claim 14, wherein at least one pixel of the first or second pixel arrays is a color pixel, and wherein the color pixel is comprised of a plurality of monochrome pixels.

20. A method comprising:

forming at least a first pixel array and a second pixel array of an image sensor such that at least some of the pixels of the first pixel array are interspersed with the pixels of the second pixel array;

coupling the pixels of the first pixel array and the second pixel array to control logic, the control logic operable to provide an exposure of the first pixel array different from an exposure of the second pixel array; and

providing storage for image information obtained from the first pixel array and the second pixel array.

21. The method of claim 20, wherein interspersing pixels includes interspersing pixels of the first pixel array and the second pixel array in an alternating arrangement.

22. The method of claim 20, wherein interspersing pixels includes interspersing pixels of the first pixel array and the second pixel array in a checkerboard arrangement.

23. The method of claim 20, wherein the control logic is operable to allow the exposure of the first pixel array to begin before the exposure of the second pixel array begins.

24. The method of claim 20, wherein the control logic is operable to allow the exposure of the first pixel array to end before the exposure of the second pixel array ends.

25. The method of claim 20, wherein the control logic is operable to allow the exposure of the first pixel array to bracket the exposure of the second array.

26. The method of claim 20, wherein the control logic is operable to allow the exposure of the first pixel array to end before the exposure of the second pixel array begins.

27. The method of claim 20, wherein the control logic is operable to allow a duration of time to occur between the exposure of the first pixel array and the exposure of the second pixel array.

28. The method of claim 20, wherein the control logic is operable to allow the exposure of at least the first pixel array to occur in relation to an illumination of a flash.

29. The method of claim 28, wherein the control logic is operable to allow the exposure of the first pixel array to occur before the flash begins and the exposure of the second array to occur during the flash.

31. A computer readable storage medium including program code for a microprocessor to execute embodiments of a method comprising:

exposing at least one pixel array and another pixel array to an image, wherein at least some of the pixels of the one pixel array are interspersed with pixels of the other pixel array, and wherein the exposure of the one pixel array is different from the other pixel array; and

combining image information obtained from the pixel arrays.

32. The computer readable storage medium of claim 31, further including program code for replacing empty pixels, or saturated pixels, or both, from one pixel array with image information from adjacent pixel locations of another pixel array where the corresponding adjacent pixel is neither empty nor saturated.

33. The computer readable storage medium of claim 31, wherein the pixel arrays include pixel clusters, at least some of adjacent pixel clusters of the one pixel array are interspersed with pixel clusters of the other pixel array, and wherein combining image information includes combining image information from adjacent pixel clusters of the one and the other pixel arrays.