Light emitting device methods

• US 20060141648A1
• Filed: 12/23/2005
• Published: 06/29/2006
• Est. Priority Date: 04/15/2003
• Status: Active Grant

• Current Assignee: Luminus Devices Incorporated (Sanan Optoelectronics Company Limited)
• Original Assignee: Luminus Devices Incorporated (Sanan Optoelectronics Company Limited)
• Inventors: Erchak, Alexei A., Brown, Michael Gregory, Graff, John W., Duncan, Scott W., Minsky, Milan S.
• Granted Patent: US 7,521,273 B2
• Time in Patent Office: Days
• US Class Current: 438/29
• CPC Class Codes: H01L 2933/0083 Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate

Abstract

Light-emitting device methods are disclosed.

Claims

1-82. -82. (canceled)

83. A method of making a light emitting device, the method comprising:

providing a first multi-layer stack, comprising;

a substrate;

a submount, and

a semiconductor layer between the substrate and the submount, the semiconductor layer being supported by the submount wherein the semiconductor layer and submount are selected so that a coefficient of thermal expansion of the submount differs from a coefficient of thermal expansion of the semiconductor layer by less than about 15%; and

exposing the semiconductor layer to electromagnetic radiation to partially decompose the semiconductor layer; and

removing the substrate from the first multi-layer stack to form a second multi-layer stack.

84. The method of claim 83, wherein the thermal expansion of the submount differs from the coefficient of thermal expansion of the semiconductor layer by less than about 10%.

85. The method of claim 83, wherein the coefficient of thermal expansion of the submount differs from the coefficient of thermal expansion of the semiconductor layer by less than about 5%.

86. The method of claim 83, wherein a thickness of the submount is greater than a thickness of the substrate.

91. The method of claim 83, wherein the wafer has a cross-sectional area of at least about two inches.

92. The method of claim 83, wherein the wafer has a cross-sectional area of at least about four inches.

93. The method of claim 83, wherein the wafer has a cross-sectional area of at least about 12 inches.

94. The method of claim 83, wherein the semiconductor layer comprises a III-V semiconductor layer.

95. The method of claim 94, wherein the III-V semiconductor layer comprises a nitride.

96. The method of claim 95, wherein the III-V semiconductor layer comprises a gallium nitride compound.

97. The method of claim 95, wherein the III-V semiconductor layer is selected from the group consisting of gallium nitride, aluminum gallium nitride, aluminum indium gallium nitride, indium gallium nitride, and combinations thereof.

98. The method of claim 97, wherein the submount comprises a material selected from the group consisting of germanium, silicon, silicon-carbide, copper, copper-tungsten, diamond, nickel-cobalt, and combinations thereof.

99. The method of claim 83, wherein the submount comprises a material selected from the group consisting of germanium, silicon, silicon-carbide, copper, copper-tungsten, diamond, nickel-cobalt, and combinations thereof.

100. The method of claim 83, wherein the submount is sputtered.

101. The method of claim 83, wherein the submount is electroformed.

102. The method of claim 83, wherein the substrate comprises a material selected from the group consisting of sapphire, a compound semiconductor, zinc oxide, silicon carbide, silicon, and combinations thereof.

103. The method of claim 83, wherein the electromagnetic radiation includes an absorption wavelength of the semiconductor layer.

104. The method of claim 103, wherein the electromagnetic radiation includes radiation at about 248 nanometers.

105. The method of claim 103, wherein the electromagnetic radiation includes radiation at about 355 nanometers.

106. The method of claim 83, wherein the multi-layer stack includes a quantum well-containing region, and a peak output wavelength of the quantum well-containing region changes as the substrate is exposed to the electromagnetic radiation.

107. The method of claim 106, wherein the peak output wavelength increases as the substrate is exposed to the electromagnetic radiation.

108. The method of claim 83, wherein the semiconductor layer is exposed to the electromagnetic radiation through the substrate.

109. The method of claim 108, further comprising exposing multiple portions of the substrate to the electromagnetic radiation in the form of a pattern on the surface of the substrate.

110. The method of claim 109, wherein the multiple portions of the substrate are simultaneously exposed to the electromagnetic radiation.

111. The method of claim 109, wherein at least some of the multiple portions of the substrate are exposed to the electromagnetic radiation at different times.

112. The method of claim 109, wherein the pattern is selected from the group consisting of serpentine patterns, circular patterns, spiral patterns, grids, gratings, triangular patterns, elementary patterns, random patterns, complex patterns, periodic patterns, nonperiodic patterns, and combinations thereof.

113. The method of claim 109, further comprising, before exposing the substrate to the electromagnetic radiation, passing the electromagnetic radiation through a mask.

114. The method of claim 113, wherein the mask is configured within an optical system.

115. The method of claim 113, wherein the mask is supported by the surface of the substrate.

116. The method of claim 115, wherein the mask is formed by a lithography process.

117. The method of claim 113, wherein the multiple portions of the substrate are simultaneously exposed to the electromagnetic radiation.

118. The method of claim 113, wherein the electromagnetic radiation is rastered across the mask.

119. The method of claim 109, wherein the electromagnetic radiation is rastered across the surface of the substrate.

120. The method of claim 83, wherein the method creates substantially no cracks in the semiconductor layer.

121. The method of claim 83, wherein the semiconductor layer is a portion of a multi-layer stack, and the method creates substantially no cracks in the layers in the multi-layer stack.

122. The method of claim 83, further comprising heating the multi-layer stack while exposing the substrate to the electromagnetic radiation.

123. The method of claim 122, wherein said heating uses a source of electromagnetic radiation different than that used to expose the multilayer stack.

124. The method of claim 83, further comprising vibrating the first multi-layer stack while exposing the substrate to the electromagnetic radiation.

125. The method of claim 83, further comprising heating the multi-layer stack after exposing the substrate to the electromagnetic radiation.

126. The method of claim 83, further comprising, after removing the substrate, treating the semiconductor layer.

127. The method of claim 126, wherein treating the semiconductor layer removes the semiconductor layer.

128. The method of claim 126, wherein treating the semiconductor layer includes a chemical-mechanical polishing process.

129. The method of claim 126, wherein treating the semiconductor layer includes mechanical polishing.

130. The method of claim 126, wherein treating the semiconductor layer includes dry etching.

131. The method of claim 126, wherein treating the semiconductor layer includes dry etching with a substantially chemical etching component.

132. The method of claim 126, wherein treating the semiconductor layer includes a substantially physical etching component.

133. The method of claim 126, wherein treating the semiconductor layer includes wet etching.

134. The method of claim 126, wherein the semiconductor layer is a buffer layer, and treating the semiconductor layer includes removing the semiconductor layer to expose a surface of an n-doped semiconductor layer, the buffer layer being supported by the n-doped semiconductor layer before removal of the buffer layer.

135. The method of claim 134, wherein removing the substrate from the first multi-layer stack results in formation of a residue on a surface of the buffer layer.

136. The method of claim 135, wherein the residue comprises one or more constituents of the substrate.

137. The method of claim 135, wherein the residue comprises aluminum.

138. The method of claim 137, wherein the residue further comprises oxygen.

139. The method of claim 135, wherein treating the semiconductor layer includes removing the residue.

140. The method of claim 134, further comprising forming a dielectric function that varies spatially according to a pattern in the exposed surface of the n-doped semiconductor layer.

141. The method of claim 134, further comprising roughening the exposed surface of the n-doped semiconductor layer.

142. The method of claim 141, wherein the pattern extends into the n-doped semiconductor layer, and the method further comprises roughening an exposed portion of the pattern that extends into the n-doped semiconductor layer.

143. The method of claim 83, wherein the semiconductor layer is a buffer layer that is supported by an n-doped semiconductor layer, and the method includes removing the buffer layer to expose a surface of the n-doped semiconductor layer.

144. The method of claim 83, wherein removing the substrate from the first multi-layer stack results in formation of a residue on a surface of the buffer layer.

145. The method of claim 144, wherein the residue comprises one or more constituents of the substrate.

146. The method of claim 144, wherein the residue comprises aluminum.

147. The method of claim 146, wherein the residue further comprises oxygen.

148. The method of claim 83, wherein the submount is formed by a process selected from the group consisting of plating processes, sputter deposition processes, electroforming, and combinations thereof.

149. The method of claim 83, wherein the submount has acoustically absorbing platform.

150. The method of claim 83, wherein the acoustically absorbing platform comprises a material selected from the group consisting of polymers, metallic foams and conformable metals.

151. The method of claim 83, wherein the substrate is treated prior to being exposed to the electromagnetic radiation.

152. The method of claim 151, wherein treating the substrate includes a process selected from the group consisting of etching the substrate, polishing the substrate, grinding the substrate, sandblasting the substrate, and combinations thereof.

153. The method of claim 151, wherein treating the substrate includes patterning the substrate.

154. The method of claim 151, wherein treating the substrate includes depositing an antireflection coating on the substrate.

155. The method of claim 83, wherein the second multi-layer stack includes a p-doped semiconductor layer, and prior to the removal of the substrate a neutral mechanical axis of the multi-layer stack is located substantially close to an interface between the p-doped semiconductor layer and the surface of the submount.

156. The method of claim 83, wherein the second multi-layer stack includes a bonding layer between the submount and the p-doped semiconductor layer, and the substrate is etched so that a neutral mechanical axis of the second multi-layer stack is located at an interface between the p-doped semiconductor layer and the bonding layer.

157. The method of claim 83, wherein the second multi-layer stack includes a bonding layer between the submount and the p-doped semiconductor layer, and the submount is etched so that a neutral mechanical axis of the second multi-layer stack is located at an interface between the p-doped semiconductor layer and the bonding layer.

158. The method of claim 83, wherein portions of the substrate are separately removed.

159. The method of claim 158, wherein overlapping fields of the substrate are exposed to the electromagnetic radiation.

160. The method of claim 83, wherein the first multi-layer stack further comprises a p-doped semiconductor layer between the submount and the semiconductor layer.

161. The method of claim 160, wherein the p-doped semiconductor layer is bonded to the submount via at least one bonding layer.

162. The method of claim 160, wherein the first multi-layer stack further comprises an active region between the p-doped semiconductor layer and the semiconductor layer.

163. The method of claim 83, wherein a thickness of the submount is greater than a thickness of the substrate.

164. The method of claim 83, wherein the semiconductor layer comprises a portion of a layer, the layer also having an n-doped semiconductor portion.

165. The method of claim 83, wherein the electromagnetic radiation forms an image on the surface of the substrate that has at least one dimension that is at most about one millimeter.

166. The method of claim 165, wherein the at least one dimension is at most about 100 microns.

167. The method of claim 83, wherein the second multi-layer stack includes a bonding layer.

168. The method of claim 167, wherein the bonding layer comprises a gold-tin alloy.

169. The method of claim 167, wherein the bonding layer comprises a material selected from the group consisting of gold-tin alloys, indium, and palladium-indium alloys.

87. A method of making a light emitting device, the method comprising:

providing a first multi-layer stack, comprising;

a substrate;

a submount that is thicker than the substrate; and

a semiconductor layer between the substrate and the submount, the semiconductor layer being supported by the submount, wherein the semiconductor layer and submount are selected so that a coefficient of thermal expansion of the submount differs from a coefficient of thermal expansion of the semiconductor layer by less than about 15%; and

exposing the semiconductor layer to electromagnetic radiation to partially decompose the semiconductor layer; and

removing the substrate from the first multi-layer stack to form a second multi-layer stack.

88. The method of claim 87, wherein the submount is at least about 10 microns thick.

89. The method of claim 87, wherein the submount is at most about five millimeters thick.

90. The method of claim 87, wherein the substrate is at most about one millimeter thick.

170. A method of making a light emitting device, the method comprising:

providing a first multi-layer stack in the form of a wafer, comprising;

a substrate;

a submount; and

a semiconductor layer between the substrate and the submount, the semiconductor layer supported by the substrate, wherein the substrate and the submount are selected so that a coefficient of thermal expansion of the submount differs from a coefficient of thermal expansion of the substrate by less than about 15%; and

exposing the semiconductor layer to electromagnetic radiation to partially decompose the semiconductor layer; and

removing the substrate from the first multi-layer stack to form a second multi-layer stack.

171. The method of claim 170, wherein the submount and the semiconductor layer are selected so that a coefficient of thermal expansion of the submount differs from a coefficient of thermal expansion of the semiconductor layer by less than about 10%.

172. The method of claim 170, wherein the submount and the semiconductor layer are selected so that a coefficient of thermal expansion of the submount differs from a coefficient of thermal expansion of the semiconductor layer by less than about 5%.

173. The method of claim 170, wherein a thickness of the submount is greater than a thickness of the substrate.