Liquid crystal display device and fabricating method thereof

• US 20060146256A1
• Filed: 12/21/2005
• Published: 07/06/2006
• Est. Priority Date: 12/31/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul
• Granted Patent: US 7,733,453 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/13629 Multilayer wirings

Abstract

A fringe field switching thin film transistor substrate includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode opposed to the pixel electrode and a semiconductor layer defining a channel between the source electrode and the drain electrode. A common electrode extends from the common line into the pixel area. A pixel electrode extends from the drain electrode into the pixel area overlapping the common electrode with the gate insulating film. The gate line and the common line are formed from a first conductive layer group having double conductive layers, and the common electrode is formed by an extension of the lowermost layer of the common line. The data line, the source electrode and the drain electrode are formed of a second conductive layer group having double conductive layers.

Claims

1. A liquid crystal display device, comprising:

a gate line provided on a substrate;

a data line crossing the gate line with a gate insulating film to define a pixel area;

a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode opposed to the pixel electrode and a semiconductor layer for defining a channel between the source electrode and the drain electrode;

a common line provided in parallel to the gate line on the substrate;

a common electrode extended from the common line into the pixel area; and

a pixel electrode extended from the drain electrode into the pixel area in such a manner as to overlap the common electrode with the gate insulating film,

wherein the gate line and the common line are formed of a first conductive layer group having at least double conductive layers, and the common electrode is formed by an extension of the lowermost layer of the common line; and

wherein the data line, the source electrode and the drain electrode are formed of a second conductive layer group having at least double conductive layers, and the pixel electrode is formed by an extension of the lowermost layer of the drain electrode.

2. The device as claimed in claim 1, wherein a storage capacitor is provided by an overlapping of the drain electrode with the common electrode.

3. The device as claimed in claim 1, wherein the common electrode has a plate shape, and the pixel electrode has a rib shape.

4. The device as claimed in claim 1, further comprising:

a gate pad connected to the gate line;

a data pad to be connected to the data line; and

a common pad connected to the common line,

wherein each of the gate pad, the data pad and the common pad includes;

a lower pad electrode formed of the first conductive layer group;

a contact hole passing through the gate insulating film to expose the lower pad electrode; and

an upper pad electrode connected to the lower pad electrode via the contact hole and formed of the lowermost layer of the second conductive layer group.

5. The device as claimed in claim 4, further comprising:

a data link provided such that the first conductive layer group is extended from a lower electrode of the data pad to have a portion thereof overlapped with the data line; and

a second contact hole passing through the gate insulating film to connect the data line to the data link.

6. The device as claimed in claim 5, wherein the second contact hole is formed in an area to be sealed by the sealant.

7. The device as claimed in claim 5, further comprising:

an alignment film on the data line, the source electrode, the drain electrode and the pixel electrode.

8. The device as claimed in claim 7, wherein the second contact hole is formed under the alignment film.

9. The device as claimed in claim 1, wherein the semiconductor pattern is formed at a position to be provided with the thin film transistor.

10. The device as claimed in claim 1, wherein each of the first and second conductive layers includes a lowermost layer having a transparent conductive layer and an upper layer having at least one of a single layer formed of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, a Mo-alloy, a Cu-alloy or an Al-alloy, a double layer and a triple layer formed of Al/Cr, Al/Mo, Al(Nd)/Al, Al(Nd)/Cr, Mo/Al(Nd)/Mo, Cu/Mo, Ti/Al(Nd)/Ti, Mo/Al, Mo/Ti/Al(Nd), Cu-alloy/Mo, Cu-alloy/Al, Cu-alloy/Mo-alloy, Cu-alloy/Al-alloy, Al/Mo-alloy, Mo-alloy/Al, Al-alloy/Mo-alloy, Mo-alloy/Al-alloy, and Mo/Al-alloy.

11. The device as claimed in claim 1, wherein the first conductive group has step coverage having a stepwise shape.

12. The device as claimed in claim 1, wherein the second conductive group has step coverage having a stepwise shape.

13. A method of fabricating a liquid crystal display device, comprising:

a first mask process forming a first mask pattern group including a gate line, a gate electrode connected to the gate line and a common line parallel to the gate line having a first conductive layer group structure of at least double conductive layers, and a common electrode formed by an extension of the lowermost layer of the common line having a single layer structure on a substrate;

a second mask process forming a gate insulating film on the first mask pattern group and a semiconductor pattern on the gate insulating film; and

a third mask process forming a third mask pattern group including a data line, a source electrode connected to the data line and a drain electrode opposed to the source electrode having a second conductive layer group structure of at least double conductive layers, and a pixel electrode formed by an extension of the lowermost layer of the drain electrode with being overlapped with the common electrode having a single layer structure, on the gate insulating film provided with the semiconductor pattern at an area to be sealed by the sealant.

14. The method as claimed in claim 13, further comprising:

forming an alignment film on the third mask pattern group.

15. The method as claimed in claim 13, wherein the first mask process includes forming a lower pad electrode to be connected to at least one of the gate line, the data line and the common line from the first conductive layer group,

the second mask process includes forming a contact hole passing through the gate insulating film to expose the lower pad electrode, and

the third mask process includes forming an upper pad electrode to be connected, via the contact hole, to the lower pad electrode from the lowermost layer of the second conductive layer group.

16. The method as claimed in claim 15, wherein the first mask process includes forming a data link provided such that the first conductive layer group is extended from the lower pad electrode to be overlapped with the data line, and

the second mask process includes forming a second contact hole for connecting the data link with the data line.

17. The method as claimed in claim 16, wherein the first mask process includes:

forming the first conductive layer group on the substrate;

forming a different thickness of the first and second photo-resist patterns by a photolithography using one of a half tone mask and a diffractive exposure mask;

forming the first mask pattern group including the common electrode having said second conductive layer group structure by an etching process using the first and second photo-resist patterns;

removing the second photo-resist pattern and etching the exposed common electrode to remain the lowermost layers thereof; and

removing the first photo-resist pattern.

18. The method as claimed in claim 16, wherein the second mask process includes:

forming a gate insulating film, an amorphous silicon layer and an amorphous silicon layer doped with an impurity on the first mask pattern group;

forming a different thickness of the first and second photo-resist patterns by a photolithography using one of a half tone mask and a diffractive exposure mask; and

forming the contact holes by an etching process using the first and second photo-resist patterns;

removing the second photo-resist pattern and forming the semiconductor pattern by an etching process using the first photo-resist pattern; and

removing the first photo-resist pattern.

19. The method as claimed in claim 16, wherein the third mask process includes:

forming the second conductive layer group on the gate insulating film provided with the semiconductor pattern;

forming a different thickness of the first and second photo-resist patterns using one of a half tone mask and a diffractive exposure mask;

patterning the second conductive layer group by an etching process using the first and second photo-resist patterns to provide a third mask pattern group including the upper pad electrode;

removing an amorphous silicon layer doped with an impurity exposed between the source electrode and the drain electrode; and

removing the second photo-resist pattern and etching the exposed upper pad electrode to remain the lowermost layers thereof; and

removing the first photo-resist pattern.

20. The method as claimed in claim 17, each of the first and second conductive layers includes a lowermost layer having a transparent conductive layer and an upper layer having at least one of a single layer formed of a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, a Mo-alloy, a Cu-alloy or an Al-alloy, a double layer and a triple layer formed of Al/Cr, Al/Mo, Al(Nd)/Al, Al(Nd)/Cr, Mo/Al(Nd)/Mo, Cu/Mo, Ti/Al(Nd)/Ti, Mo/Al, Mo/Ti/Al(Nd), Cu-alloy/Mo, Cu-alloy/Al, Cu-alloy/Mo-alloy, Cu-alloy/Al-alloy, Al/Mo-alloy, Mo-alloy/Al, Al-alloy/Mo-alloy, Mo-alloy/Al-alloy, and Mo/Al-alloy.

21. The method as claimed in claim 19, further comprising:

if the lowermost layer of the second conductive layer group is over-etched in comparison to the upper layer thereof when the second conductive group is patterned, then etching each side of the upper layer exposed through the second photo-resist pattern to locate the edge of the upper layer at an inner side than that of the lowermost layer.

22. The method as claimed in claim 13, wherein at least two layers of the semiconductor pattern, the source electrode, the drain electrode and the pixel electrode have step coverage taking a stepwise shape.

23. The method as claimed in claim 16, wherein the second contact hole is formed in an area to be sealed by the sealant.

24. The method as claimed in claim 14, wherein the first mask process includes forming a lower pad electrode to be connected to at least one of the gate line, the data line and the common line from the first conductive layer group,

the second mask process includes forming a contact hole passing through the gate insulating film to expose the lower pad electrode, and

the third mask process includes forming an upper pad electrode to be connected, via the contact hole, to the lower pad electrode from the lowermost layer of the second conductive layer group.

25. The method as claimed in claim 24, wherein the first mask process includes forming a data link provided such that the first conductive layer group is extended from the lower pad electrode to be overlapped with the data line, and

the second mask process includes forming a second contact hole for connecting the data link with the data line.

26. The method as claimed in claim 25, wherein the second contact hole is formed under the alignment film.

27. The method as claimed in claim 13, wherein the first conductive group has step coverage having a stepwise shape.

28. The method as claimed in claim 13, wherein the second conductive group has step coverage having a stepwise shape.