Multi-level ONO flash program algorithm for threshold width control

• US 20060152974A1
• Filed: 01/13/2005
• Published: 07/13/2006
• Est. Priority Date: 01/13/2005
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Hamilton, Darlene, Bathul, Fatima, Horiike, Masato
• Granted Patent: US 7,130,210 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough. Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

Claims

1. A method of programming one or more memory bits on a wordline of a multi-level flash memory array, the memory bits having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:

providing one or more unprogrammed multi-level flash memory bits to be programmed;

performing a rough programming operation on the memory bits of the array until the threshold voltage of each of the memory bits generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and

performing a fine programming operation on the memory bits of the array until the threshold voltage of each memory bit generally corresponds to the target threshold voltage.

2. The method of claim 1, wherein each memory bit of the multi-level flash memory array comprises four data levels.

3. The method of claim 1, wherein the memory cells of the multi-level flash memory array comprise dual sided ONO flash memory cells having three or more data levels per bit.

4. The method of claim 1, further comprising generating a dynamic fast-bit drain voltage for each of the program levels on the wordline.

5. The method of claim 4, wherein the generating a dynamic fast-bit drain voltage for each of the program levels on the wordline comprises:

selecting groups of sample bits from the wordline associated with each program level;

selecting a starting drain voltage for each program level from the lowest allowable drain voltage for each program level;

applying program pulses to a first group of sample bits associated with a first program level;

increasing one of the drain voltage, a gate voltage, and a combination of the drain and gate voltages of the first group of sample bits;

determining a first drain voltage at which a fast-bit of the group of sample bits is programmed or a maximum drain voltage level is attained; and

reselecting another group of sample bits associated with a program level, applying program pulses, increasing one of the drain and gate voltages until a fast-bit drain voltage is determined for each group of sample bits associated with a respective program level.

6. The method of claim 1, wherein the rough programming operation comprises:

setting a program verify value to correspond to the rough threshold voltage;

selecting a predetermined programming profile of drain and gate voltages for programming the bits based on a program pattern of the cell bit-pairs;

applying a programming pulse to the bits according to the programming profile;

reapplying programming pulses to the bits according to the programming profile until the threshold voltage of each bit of the memory cells generally corresponds to the rough threshold voltage of the program verify value; and

deselecting the rough programmed bits.

7. The method of claim 6, further comprising alternately applying the programming pulses to each bit of the memory cell bit-pairs in order to obtain improved CBD control.

8. The method of claim 6, wherein the predetermined programming profile comprises a predetermined pattern of the drain and gate voltages that are applied to the bits over successive programming pulses.

9. The method of claim 8, wherein the predetermined programming profile further varies one of the drain voltage, the gate voltage, and a combination of the drain and gate voltages from an initial rough start drain voltage and an initial rough start gate voltage relative to a dynamic fast-bit drain voltage generated for each of the program levels on the wordline.

10. The method of claim 8, wherein the predetermined programming profile provides a rough start drain voltage, and an upper drain voltage based on a predetermined number of program pulses offset relative to the dynamic fast-bit drain voltage.

11. The method of claim 8, wherein the predetermined pattern of the drain and gate voltages comprise successive programming pulses that change by about 50 mV to about 200 mV per pulse.

12. The method of claim 8, wherein the predetermined pattern of the drain and gate voltages comprise programming pulses of about 150 ns-2 μ

s width.

13. The method of claim 1, wherein the rough and fine programming operations comprise programming pulses of drain and gate voltages applied to the bits, and wherein the programming pulses of the rough and fine programming operations have about the same pulse width and about the same step amplitude.

14. The method of claim 6, wherein the program pattern of the cell bit-pairs comprises the program levels of all the bits of the memory cells.

15. The method of claim 6, wherein all the cell bit-pairs selected on the wordline have the same program patterns.

16. The method of claim 1, wherein the fine programming operation comprises:

setting a program verify value to correspond to the target threshold voltage;

selecting a predetermined programming profile of drain and gate voltages for programming the bits based on a program pattern of the cell bit-pairs;

applying a programming pulse to the bits according to the programming profile;

reapplying programming pulses to the bits according to the programming profile until the threshold voltage of each bit of the memory cells generally corresponds to the fine threshold voltage of the program verify value; and

deselecting the fine programmed bits.

17. The method of claim 16, further comprising alternately applying the programming pulses to each bit of the memory cell bit-pairs in order to obtain improved CBD control.

18. The method of claim 16, wherein the predetermined programming profile comprises a predetermined pattern of the drain and gate voltages that are applied to the memory bits over successive programming pulses.

19. The method of claim 18, wherein the predetermined programming profile further varies one of the drain voltage, the gate voltage, and a combination of the drain and gate voltages relative to an initial fine start drain voltage and an initial fine start gate voltage.

20. The method of claim 19, wherein the initial fine start drain voltage is about the level of the rough start drain voltage or higher.

21. The method of claim 16, wherein the program pattern of the cell bit-pairs comprises the program levels of all the bits of the memory cells.

22. The method of claim 16, wherein all the cell bit-pairs selected on the wordline have the same program patterns.

23. The method of claim 1, further comprising selecting all of the bits on the wordline that are to have the bit-pairs programmed to the same program pattern.

24. The method of claim 1, wherein all the cell bit-pairs selected on the wordline have the same program patterns, and wherein the predetermined programming profile comprises a predetermined pattern of the drain and gate voltages that are applied to the memory bits over successive programming pulses based on the program pattern of the cell bit-pairs selected.

25. The method of claim 24, wherein the programming profile is determined by a look-up table corresponding to the program pattern of the cell bit-pairs.

26. The method of claim 24, wherein one of the drain voltage and the gate voltage is held constant while the other of the voltages follows the programming profile.

27. The method of claim 24, wherein the drain voltage and the gate voltage follow the programming profile.

28. The method of claim 1, wherein the rough threshold voltage is offset lower than the target threshold voltage by about 150-450 mV.

29. A method of programming one or more bits of memory cell bit-pairs on a wordline of a multi-level flash memory array, the bits of the memory cells having two or more program levels and a blank level, the levels comprising three or more data levels corresponding to three or more threshold voltages, the method comprising:

providing one or more unprogrammed multi-level flash memory bits selected to be programmed to the same program pattern;

generating a dynamic fast-bit drain voltage for each of the program levels on the wordline;

performing a rough programming operation on the bits of the array based on one of the fast-bit drain voltages and the cell program pattern until the threshold voltage of each bit of the memory cells generally corresponds to a rough threshold voltage that is an offset value less than a target threshold voltage; and

performing a fine programming operation on the memory bits of the array until the threshold voltage of each bit generally corresponds to the target threshold voltage.

30. The method of claim 29, wherein the bits of the memory cells of the multi-level flash memory array comprise three or more data-levels.

31. The method of claim 29, wherein the memory cells of the multi-level flash memory array comprise dual sided ONO three or more data-levels per bit flash memory cells.

32. The method of claim 29, wherein the generating a dynamic fast-bit drain voltage for each of the two or more program levels on the wordline comprises:

selecting groups of sample bits from the wordline associated with each program level;

selecting a starting drain voltage for each program level from the lowest allowable drain voltage for each program level;

applying program pulses to a first group of sample bits associated with a first program level;

increasing one of the drain voltage, a gate voltage, and a combination of the drain and gate voltages of the first group of sample bits;

determining a first drain voltage at which a fast-bit of the group of sample bits is programmed or a maximum drain voltage level is attained; and

reselecting another group of sample bits associated with a program level, applying program pulses, increasing one of the drain and gate voltages until a fast-bit drain voltage is determined for each group of sample bits associated with a respective program level.

33. The method of claim 29, wherein the rough programming operation comprises:

setting a program verify value to correspond to the rough threshold voltage;

selecting a predetermined programming profile of drain and gate voltages for programming the bits based on a program pattern of the cell bit-pairs;

applying a programming pulse to the bits according to the programming profile;

reapplying programming pulses to the bits according to the programming profile until the threshold voltage of each bit of the memory cells generally corresponds to the rough threshold voltage of the program verify value; and

deselecting the rough programmed bits.

34. The method of claim 33, further comprising alternately applying the programming pulses to each bit of the memory cell bit-pairs in order to obtain improved CBD control.

35. The method of claim 33, wherein the predetermined programming profile comprises a predetermined pattern of the drain and gate voltages that are applied to the memory bits over successive programming pulses.

36. The method of claim 35, wherein the predetermined programming profile further varies one of the drain voltage, the gate voltage, and a combination of the drain and gate voltages from an initial rough start drain voltage and an initial rough start gate voltage relative to a dynamic fast-bit drain voltage generated for each of the two or more program levels on the wordline.

37. The method of claim 35, wherein the predetermined programming profile provides a rough start drain voltage, and an upper drain voltage based on a predetermined number of program pulses offset relative to the dynamic fast-bit drain voltage.

38. The method of claim 35, wherein the predetermined pattern of the drain and gate voltages comprise successive programming pulses that change by about 50 mV to about 200 mV per pulse.

39. The method of claim 35, wherein the predetermined pattern of the drain and gate voltages comprise programming pulse width of about 150 ns-2 μ

s.

40. The method of claim 33, wherein the program pattern of the cell bit-pairs comprises the program levels of all the bits of the memory cells.

41. The method of claim 29, wherein the fine programming operation comprises:

setting a program verify value to correspond to the target threshold voltage;

selecting a predetermined programming profile of drain and gate voltages for programming the bits based on a program pattern of the cell bit-pairs;

applying a programming pulse to the bits according to the programming profile;

reapplying programming pulses to the bits according to the programming profile until the threshold voltage of each bit of the memory cells generally corresponds to the fine threshold voltage of the program verify value; and

deselecting the fine programmed bits.

42. The method of claim 41, further comprising alternately applying the programming pulses to each bit of the memory cell bit-pairs in order to obtain improved CBD control.

43. The method of claim 41, wherein the predetermined programming profile comprises a predetermined pattern of the drain and gate voltages that are applied to the memory bits over successive programming pulses.

44. The method of claim 43, wherein the predetermined programming profile further varies one of the drain voltage, the gate voltage, and a combination of the drain and gate voltages relative to an initial fine start drain voltage and an initial fine start gate voltage.

45. The method of claim 43, wherein the initial fine start drain voltage is about the level of the rough start drain voltage or greater.

46. The method of claim 41, wherein the program pattern of the cell bit-pairs comprises the program levels of all the bits of the memory cells.

47. The method of claim 29, wherein all the cell bit-pairs selected on the wordline have the same program patterns, and wherein the predetermined programming profile comprises a predetermined pattern of the drain and gate voltages that are applied to the memory bits over successive programming pulses based on the program pattern of the cell bit-pairs selected.

48. The method of claim 47, wherein the programming profile is determined by a look-up table corresponding to the program pattern of the cell bit-pairs.

49. The method of claim 47, wherein one of the drain voltage and the gate voltage is held constant while the other of the voltages follows the programming profile.

50. The method of claim 47, wherein the drain voltage and the gate voltage follow the programming profile.

51. The method of claim 29, wherein the rough threshold voltage is offset lower than the target threshold voltage by about 150-450 mV.

52. The method of claim 29, wherein an intermediate programming operation is utilized having an intermediate threshold voltage value between the rough threshold voltage and the target threshold voltage value.

53. The method of claim 29, further comprising erasing a portion of the bits of the memory array prior to performing the rough programming operation.

54. The method of claim 29, wherein the programming operation increases threshold voltage levels generally corresponding to bits of respective memory cells of the sector.

55. The method of claim 29, wherein the rough and fine programming operations comprise programming pulses of drain and gate voltages applied to the memory bits, and wherein the programming pulses of the rough and fine programming operations have about the same pulse width and about the same step amplitude.