Soi structure comprising substrate contacts on both sides of the box, and method for the production of such a structure

• US 20060154430A1
• Filed: 01/30/2004
• Published: 07/13/2006
• Est. Priority Date: 01/30/2003
• Status: Active Grant

• Current Assignee: X-FAB Semiconductor Foundries AG (X-FAB Silicon Foundries SE)
• Original Assignee: X-FAB Semiconductor Foundries AG (X-FAB Silicon Foundries SE)
• Inventors: Goettlich, Wolfgang, Richter, Steffen, Nuernbergk, Dirk
• Granted Patent: US 7,195,961 B2
• Time in Patent Office: Days
• US Class Current: 438/311
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Disclosed are an arrangement and a production method for electrically connecting (20) active semiconductor structures (40) in the monocrystalline silicon layer (12) located on the front face of silicon-on-insulator semiconductor wafers (SOI; 10) to the substrate (13) located on the rear side and additional structures (13a) that are disposed therein. The electrical connection is made through the insulator layer (11).

Claims

1. A method for manufacturing an integrated circuit on and in an SOI semiconductor wafer having a front side (V) and a back side (R), wherein first structures (40, 50, 60) of active devices in an upper semiconductor layer (12) are connected with second structures (13a, 13a′

, 13c) of devices within the substrate (13) by electric connections (20, 22) which are formed through an insulating layer (11), the method comprising the following steps;

performing an ion implantation (30, 31) with highly energetic ions in certain areas (13′

, 13″

) from the front side (V) through the semiconductor layer (12), through the insulating layer (11) and into the substrate (13);

performing a temperature treatment for activating the ions implanted into the substrate (13) in accordance with the ion species implanted (30, 31);

forming the first structures (30, 40, 50, 60) at least partially in the upper single crystalline layer (12);

forming at least one via, preferably a plurality of vias (19, 21), in the insulating layer (11);

filling (20, 22) the at least one via (19, 21) in the insulating layer with a (conductive) metal;

forming—

in the area of the active structures (40, 50, 60) insulated with respect to each other—

metal conductors (15, 15′

, 15″

), which electrically connect the first structures of the front side with the second structure within the substrate (13) via the metal fillings (20, 22) in the vias.

2. The method of claim 1, wherein the insulating layer (11) is a silicon dioxide layer.

3. The method of claims 1 and 2, wherein a single insulating layer (11) is provided, through which the metal filling extends.

4. The method of claim 1, wherein the upper layer (12) is a thin layer with respect to the substrate (13) of the SOI wafer (10).

5. The method of claim 1, wherein the main steps of the method are performed in the described order.

6. The method of claim 1, wherein devices below the insulating layer (11) are formed by using templates and different ion species (30, 31).

7. The method of claim 1, wherein the implanted ions are activated in a plurality of steps with a different temperature.

8. The method of claim 1, wherein the vias are formed at locations at which no active single crystalline layer (12) is present (in the form of lateral insulation areas).

9. The method of claim 1, wherein the upper semiconductor layer (12) is comprised of silicon.

10. The method of claims 1 or 2, wherein the first structures (40) are at least partially formed in the upper silicon layer.

11. The method of any of the preceding claims, wherein the substrate (13) is comprised of a single crystalline silicon.

12. The method of any of the preceding claims, wherein simultaneously with the process of forming the at least one filling (metal bridge) of the at least one via (19, 21), an ohmic contact (13B) or a conductive conductor to the substrate is formed.

13. The method of any of claims 1 to 11, wherein simultaneously with the process of forming the filling (metal bridge) of the at least one via (19, 21), a Schottky contact (13C) is formed with the substrate (13).

14. The method of claim 1, wherein two first structures for two first devices (40, 50) above the insulating layer (11) are separated and insulated by at least one trench (12a, 12b, 12c), which extends to the insulating layer.

15. The method of claim 1, wherein a back side metallization (14) is formed on the back side (R).

16. The method of claim 1, wherein the metallic conductors (15, 15′

) are metallization layers.

17. The method of claim 16, wherein the conductors are provided in the form of metal bridges on at least two non-identical levels above the insulating layer (11).

18. A device assembly formed or manufacturable on the basis of the method according to one of the preceding claims.

19. The device assembly of claim 18, wherein active devices, such as diodes, MOSFETs, bipolar transistors, thyristors, and IGBTs are provided in the substrate (13) individually or in combination.

20. The device assembly of claims 18 or 19, wherein (also) structures for passive devices, such as capacitors, resistors or a shielding layer (13a″

) are provided within the substrate (13).

25. The method of any of the preceding claims, wherein the substrate is comprised of a single crystalline silicon wafer.

26. The method of any of the preceding claims, wherein along with the process of forming the metal bridge of the via also an ohmic contact to the substrate is formed.

21. A method for forming an integrated circuit on SOI semiconductor wafers, in which the active device structures in the thin upper semiconductor layer are connected with device structures within the substrate by means of electrical connections that are formed through the insulating layer, characterized in that the sequence of main steps listed below is performed on the basis of (per se known) method steps:

in specified areas, performing an ion implantation with highly energetic ions from the front side through the single crystalline semiconductor layer and the insulating layer into the substrate if necessary by using templates and different ion species as are usually used for forming devices;

performing a temperature treatment for activating the implanted ions if necessary in several steps of different temperature, adapted to the ion species implanted;

forming the device structures in the thin upper single crystalline silicon layer;

forming the vias in the insulating layer at locations at which no active thin single crystalline silicon layer is present (lateral insulation areas);

filling the vias in the insulating layer with a metal;

forming metallization layers that are insulated from each other within the area of the active device structures and which electrically connect the structures of the upper side with those within the substrate by means of the metal filling of the vias in the insulating layer.

22. The method of claim 21, wherein the insulating layer is a silicon dioxide layer.

23. The method of claim 21, wherein each bridge is independent.

24. The method of claim 21, wherein a back side metallization (14) is provided on the substrate (13).

27. The method of any of the claims 22 to 25, wherein along with the process of forming the metal bridge of the via also a Schottky contact with the substrate is formed.

28. A device assembly using the method of any of claims 22 to 27.

29. The device assembly of claim 28, wherein active devices, such as diodes, MOSFETs, bipolar transistors, thyristors, and IGBTs are provided individually or in combination within the substrate.

30. The device assembly of claims 28 of 29, wherein also passive structures such as capacitors, resistors and shielding layers are provided in the substrate in addition to active devices.