System and method for maintaining cache coherency in a shared memory system

• US 20060155935A1
• Filed: 12/20/2005
• Published: 07/13/2006
• Est. Priority Date: 10/01/1999
• Status: Active Grant

• Current Assignee: Andrew M. Jones, John Carey
• Original Assignee: Andrew M. Jones, John Carey
• Inventors: Carey, John, Jones, Andrew M.
• Granted Patent: US 7,228,389 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)

Abstract

A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.

Claims

1. A computer system comprising:

a memory system wherein at least a portion of the memory is designated as shared memory;

a transaction-based bus coupled to the memory system wherein the transaction-based bus includes a cache coherency transaction integrated within its transaction set;

a processor having a cache memory, the processor coupled to the memory system through the transaction based bus;

a plurality of system components other than the processor coupled to the transaction-based bus, wherein the system components access the memory system directly through the transaction based bus, but do not access the cache memory directly through the transaction based bus;

a request issued by one of the plurality of system components and addressed to the processor, wherein the request indicates a request to perform a cache coherency operation; and

wherein the processor is configured to respond to the request by treating the request as an explicit command to perform the cache coherency operation and wherein the processor response to the request comprises directly executing the cache coherency operation.

2. A computer system comprising:

a memory system wherein at least a portion of the memory is designated as shared memory;

a transaction-based bus coupled to the memory system wherein the transaction-based bus includes a cache coherency transaction defined within its transaction set;

a processor having a cache memory, the processor coupled to the memory system through the transaction based bus;

a plurality of system components other than the processor coupled to the transaction-based bus, wherein the system components access the memory system directly through the transaction based bus, but do not access the cache memory directly through the transaction based bus;

a request issued by one of the plurality of system components and addressed to the processor, wherein the request indicates a request to perform a cache coherency operation; and

wherein the processor is configured to respond to the request by treating the request as an explicit command to perform the cache coherency operation and wherein the processor is further configured to respond to the request by generating a response message addressed to the system component that initiated the request indicating a cache state.

3. A method for managing cache coherency in a shared memory system wherein the shared memory system is shared by a plurality of modules, including a processing unit, and wherein the plurality of modules, including the processing unit, are coupled to a system bus, the method comprising the steps of:

causing the processing unit to cache at least some locations of the shared memory system in a cache memory;

initiating a cache coherency transaction on the system bus using one of the plurality of modules rather than the processing unit; and

in response to the cache coherency transaction, causing the processing unit to directly execute a cache coherency operation indicating a cache memory state independent of performing further instructions on the processing unit.

4. A method for managing cache coherency in a shared memory system wherein the shared memory system is shared by a plurality of modules, including a processing unit, and wherein the plurality of modules, including the processing unit, are coupled to a system bus, the method comprising the steps of:

causing the processing unit to cache at least some locations of the shared memory system in a cache memory;

initiating a cache coherency transaction directly on the system bus using one of the plurality of modules rather than the processing unit; and

in response to the cache coherency transaction, causing the processing unit to execute a cache coherency operation; and

generating a response to the initiated cache coherency transaction using the processing unit, wherein the response is addressed to the module initiating the cache coherency transaction indicating a cache memory state.

5. At least one computer-readable medium containing a computer program product for managing cache coherency in a shared memory system wherein the shared memory system is shared by a plurality of modules, including a processing unit, and wherein the plurality of modules, including the processing unit, are coupled to a system bus, the computer program product comprising:

program code for causing the processing unit to cache at least some locations of the shared memory system in a cache memory;

program code for initiating a cache coherency transaction directly on the system bus using one of the plurality of modules rather than the processing unit;

in response to the cache coherency transaction, program code for causing the processing unit to execute a cache coherency operation; and

program code for generating a response to the initiated cache coherency transaction using the processing unit, wherein the response is addressed to the module initiating the cache coherency transaction indicating a cache memory state.

6. At least one computer-readable medium containing a computer program product for managing cache coherency in a shared memory system wherein the shared memory system is shared by a plurality of modules, including a processing unit, and wherein the plurality of modules, including the processing unit, are coupled to a system bus, the computer program product comprising:

program code for causing the processing unit to cache at least some locations of the shared memory system in a cache memory;

program code for initiating a cache coherency transaction on the system bus using one of the plurality of modules rather than the processing unit; and

in response to the cache coherency transaction, program code for causing the processing unit to directly execute a cache coherency operation indicating a cache memory state independent of performing further instructions on the processing unit.