Last line of defense ensuring and enforcing sufficiently valid/current code

• US 20060156008A1
• Filed: 01/12/2005
• Published: 07/13/2006
• Est. Priority Date: 01/12/2005
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Frank, Alexander
• Application Number:
  US11/034,377
• Publication Number:
  US 20060156008A1
• Time in Patent Office: Days
• US Class Current: 713/176
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 2221/2135 Metering
• CPC Class Codes: G06F 2221/2137 Time limited access, e.g. to a computer or data
• CPC Class Codes: G06F 2221/2139 Recurrent verification
• CPC Class Codes: G06F 2221/2153 Using hardware token as a secondary aspect

Abstract

A computer is adapted for self-validation using a dedicated validation circuit or process. The validation circuit may include a timing circuit for activating the validation process, a verification circuit for verifying the computer is in compliance with a pre-determined set of conditions and an enforcement circuit for imposing a sanction on the computer when the computer is found in a non-compliant state. The validation circuit may include cryptographic circuitry or processes for hashing and digital signature verification. The validation circuit is preferable small and portable to help ensure that the validation circuit itself is not vulnerable to a widespread attack. A self-validation method for use by a computer is also disclosed.

Claims

1. A computer configured for self-validation comprising:

a processor;

a memory coupled to the processor; and

a validation circuit coupled to the processor and the memory, the validation circuit operational to validate a characteristic of the computer and further operational to restrict the function of the computer when the validation fails.

2. The computer of claim 1, further comprising a trigger circuit for determining an interval for causing the validation circuit to validate the characteristic of the computer during the interval.

3. The computer of claim 2, wherein the interval is one of statistical, timed, and random.

4. The computer of claim 2, wherein the validation occurs at an increased frequency after the validation fails.

5. The computer of claim 1, wherein the validation circuit comprises a cryptographic capability.

6. The computer of claim 1, wherein the characteristic is one of a digitally signed software code, a hash of a memory range, an expiration of a software code, revocation of a digital signatory, and an expiration date.

7. The computer of claim 1, further comprising an enforcement circuit responsive to the validation circuit for restricting the function of the computer when the validation fails.

8. The computer of claim 1, wherein the processor comprises the validation circuit.

9. A validation circuit in a computer, the validation circuit comprising:

a triggering circuit;

a logic circuit coupled to the triggering circuit;

the logic circuit for verifying a characteristic of the computer; and

an enforcement circuit coupled to the verification circuit;

wherein the enforcement circuit, in response to a signal from the logic circuit, limits the performance of the computer.

10. The validation circuit of claim 9, further comprising a cryptography circuit wherein the logic circuit verifies the characteristic using the cryptography circuit.

11. The validation circuit of claim 9, wherein the enforcement circuit limits the performance of the computer by one of a periodic reset, a reduction in processor capacity and a reduction in display resolution.

12. The validation circuit of claim 9, wherein the triggering circuit comprises one of a clock and a random number generator.

13. The validation circuit of claim 9, the validation circuit being resistant to tampering from another component of the computer.

14. A method for authenticating a computer comprising:

providing a validation circuit;

programming the validation circuit with information corresponding to a characteristic of the computer;

programming the validation circuit to activate at an interval;

validating the characteristic of the computer; and

limiting a function of the computer when the validating the characteristic of the computer fails.

15. The method of claim 14, further comprising programming the validation circuit with a cryptographic secret.

16. The method of claim 14, wherein the validating further comprises verifying at one of a random interval and a timed interval.

17. The method of claim 14, wherein the validating further comprises one of verifying a digital signature of a code function and verifying a hash of a memory range.

18. The method of claim 14, further comprising logging a failed verification of the characteristic of the computer, and setting a non-volatile flag to be evaluated upon restart/reset of the computer.

19. The method of claim 14, wherein the limiting a function of the computer further comprises limiting a number of communication messages.

20. The method of claim 14, wherein the limiting a function of the computer further comprises one of limiting a speed of operation and limiting operation to a subset of available software executable code.