Radio frequency switch

• US 20060160520A1
• Filed: 01/14/2005
• Published: 07/20/2006
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Eudyna Devices Inc. (Sumitomo Corporation)
• Original Assignee: Eudyna Devices Inc. (Sumitomo Corporation)
• Inventors: Miyazawa, Naoyuki
• Granted Patent: US 7,561,853 B2
• Time in Patent Office: Days
• US Class Current: 455/333
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.

Claims

1. A switch comprising at least three FETs that are connected in series and select one of radio frequency signals,

one of the at least three FETs arranged at an intermediate stage having a width of a source or drain electrode narrower than widths of source or drain electrodes of other FETs arranged at initial and final stages.

2. The switch as claimed in claim 1, wherein the radio frequency switch comprises at least four FETs connected in series.

3. The switch as claimed in claim 2, wherein ones of the at least four FETs arranged on intermediate stages having widths of source or drain electrodes narrower than those of the source or drain electrodes arranged at the initial and final stages.

4. The switch as claimed in claim 1, wherein a total width of gate electrodes of the FETs except those arranged at the initial and final stages is smaller than that of gate electrodes of the FETs arranged at the initial and final stages.

5. The switch as claimed in claim 1, further comprising electrode lines that extend along gate electrodes of the at least three FETs, wherein the electrode lines of the FETs except those arranged at the initial and final stages is shorter than that of the electrode lines of the FETs arranged at the initial and final stages.