Non-volatile memory device, methods of fabricating and operating the same

• US 20060170028A1
• Filed: 12/30/2005
• Published: 08/03/2006
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong-Tae, Han, Jeong-Uk, Jeon, Hee-Seog, Yoon, Seung-Beom
• Granted Patent: US 7,492,002 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

Claims

1. A non-volatile memory device comprising:

a floating gate formed on a substrate with a gate insulation layer interposed therebetween;

a tunnel insulation layer formed on the floating gate;

a select gate electrode inducing charge through the gate insulation layer; and

a control gate electrode inducing charge tunneling through the tunnel insulation layer.

2. The non-volatile memory device of claim 1, wherein the select gate electrode is insulated from the floating gate by a dielectric layer, and the gate electrode is insulated from the floating gate by the tunnel insulation layer.

3. The non-volatile memory device of claim 2, wherein a capacitance between the select gate electrode and the floating gate is higher than a capacitance between the control gate electrode and the floating gate.

4. The non-volatile memory device of claim 3, wherein the dielectric layer includes a material having a higher dielectric constant than the tunnel insulation layer.

5. The non-volatile memory device of claim 1, wherein the floating gate has a tip formed toward the control gate electrode.

6. The non-volatile memory device of claim 5, wherein the charge tunneling through the tunnel insulation layer occurs around the tip of the floating gate.

7. The non-volatile memory device of claim 1, further comprising:

a source region and a drain region defining a channel region in a semiconductor substrate,

wherein the floating gate, the select gate electrode, and the control gate electrode are formed on the channel region with the gate insulation layer interposed therebetween.

8. The non-volatile memory device of claim 7, wherein hot carriers generated at the channel region by the induction of the select gate electrode are injected through the gate insulation layer.

9. A non-volatile memory device according to claim 1 further comprising:

a source region and a drain region defining a channel region in the substrate; and

an integrate dielectric interposed between the select gate electrode and the floating gate, and wherein the gate insulation layer is formed on the channel region;

the select gate electrode is formed on the gate insulation layer and the floating gate,

the control gate electrode is formed on a sidewall of the floating gate and the gate insulation layer is opposite to the select gate electrode, and

the tunnel insulation layer is interposed between the control gate electrode and the floating gate.

10. The non-volatile memory device of claim 9, wherein an area of the intergate dielectric between the select gate electrode and the floating gate is larger than an area of the tunnel insulation layer between the control gate electrode and the floating gate.

11. The non-volatile memory device of claim 9, wherein the select gate electrode comprises:

a top select gate electrode formed over the floating gate; and

a sidewall select gate electrode formed on a sidewall of the floating gate and the gate insulation layer opposite to the control gate electrode.

12. The non-volatile memory device of claim 11, wherein the sidewall select gate electrode and the control gate electrode are symmetrical with each other.

13. The non-volatile memory device of claim 11, wherein the intergate dielectric between the top select gate electrode and the floating gate includes a material having a higher dielectric constant than the tunnel insulation layer.

14. The non-volatile memory device of claim 13, wherein an interlayer dielectric between the sidewall select gate electrode and the floating gate is made of the same material as the tunnel insulation layer.

15. The non-volatile memory device of claim 11, wherein a spacer insulation pattern is interposed between the top select gate electrode and the sidewall select gate electrode and between the top select gate electrode and the control gate electrode.

16. A non-volatile memory device comprising:

a device isolation layer formed to define a plurality of active regions on a semiconductor substrate;

a gate insulation layer formed on the respective active regions;

a floating gate formed on the respective gate insulation layers;

a sensing line formed on the gate insulation layer and the floating gate to cross over the active regions;

a wordline formed on a sidewall of the floating gate and the gate insulation layer to cross over the active regions, the wordline being opposite to the sensing line;

an intergate dielectric interposed between the sensing line and the floating gate;

an intergate dielectric interposed between the sensing line and the floating gate; and

a tunnel insulation layer interposed between the wordline and the floating gate.

17. The non-volatile memory device of claim 16, wherein a capacitance between the floating gate and the sensing line is higher than a capacitance between the floating gate and the wordline.

18. The non-volatile memory device of claim 17, wherein the intergate dielectric includes a material having a higher dielectric constant than the tunnel insulation layer.

19. The non-volatile memory device of claim 16, wherein the sensing line comprises:

a top sensing line crossing over the floating gate; and

a sidewall sensing line crossing over the sidewall of the floating gate and the active region.

20. The non-volatile memory device of claim 19, further comprising:

a spacer insulation pattern interposed between the top sensing line and the sidewall sensing line and between the top sensing line and the wordline.

21. The non-volatile memory device of claim 19, wherein the sidewall sensing line and the wordline are symmetrical with each other.

22. The non-volatile memory device of claim 19, wherein the intergate dielectric between the top sensing line and the floating gate includes a material having a higher dielectric constant than the tunnel insulation layer.

23. The non-volatile memory device of claim 22, wherein the intergate dielectric between the sidewall sensing line and the floating gate is made of the same material as the tunnel insulation layer.

24. The non-volatile memory device of claim 16, wherein the floating gate has a tip formed toward the control gate electrode.

25. The non-volatile memory device of claim 16, further comprising:

a drain region formed in respective active regions adjacent to the sensing line; and

a common source line formed at an active region adjacent to the wordline to be connected to the wordline in parallel.

26. The non-volatile memory device of claim 16, wherein the floating gate, the sensing line, and the wordline on the active region constitute a memory cell, and the sensing line is divided into predetermined memory cell units to allow a plurality of sensing lines to corresponding to respective wordlines.

27. A method for operating a non-volatile memory device including a source region and a drain region defining a channel region, a gate insulation layer on the channel region, a floating gate on the gate insulation layer, a select gate electrode on the gate insulation layer and the floating gate, a control gate electrode on a sidewall of the floating gate and the gate insulation layer to be opposite to the select gate electrode, an intergate dielectric interposed between the select gate electrode and the floating gate, and a tunnel insulation layer interposed between the control gate electrode and the floating gate, the method comprising:

a write step in which charges are injected to the floating gate through the gate insulation layer;

a read step in which fluctuation of a threshold voltage of the channel region below the floating gate, caused by charges stored in the floating gate is sensed; and

an erase step in which tunneling of the charges stored in the floating gate is induced through the tunnel insulation layer.

28. The method of claim 27, wherein in the write step, a constant voltage (Vcc), a ground voltage (GND), a write voltage, and a turn-on voltage are applied to the source region, the drain region, the select gate electrode, and the control gate electrode, respectively to inject charges through the gate insulation layer.

29. The method of claim 28, wherein in the write step, the turn-on voltage applied to the control gate electrode is a voltage to form a channel at the channel region below the control gate electrode.

30. The method of claim 28, wherein in the write step, a write voltage is applied to enable hot carriers to be injected through the gate insulation layer between the floating gate and the channel region.

31. The method of claim 27, wherein in the read step, a ground voltage, a read voltage, a turn-on voltage, and a verify voltage are applied to the source region, the drain region, the select gate electrode, and the control gate electrode, respectively to sense data stored in the floating gate.

32. The method of claim 31, wherein in the read step, the turn-on voltage applied to the select gate electrode is a voltage to form a channel at the channel region below the select gate electrode.

33. The method of claim 31, wherein a verify voltage is applied to couple a voltage, which is higher than a write threshold voltage and lower than an erase threshold voltage, with the gate insulation layer between the floating gate and the channel region.

34. The method of claim 27, wherein in the erase step, a ground voltage is applied to the source region, the drain region, and the select gate electrode and an erase voltage is applied to the control gate electrode to induce charge tunneling occurring through the tunnel insulation layer.

35. The method of claim 34, wherein the erase voltage is applied to allow charge tunneling to occur through a tunnel insulation layer between the floating gate and the control gate electrode.

36. The method of claim 27, wherein the non-volatile memory device comprises a plurality of memory cells arranged in row and column directions,

the drain regions of the memory cells are arranged in the row direction and connected to constitute a bitline;

the select gate electrodes of the memory cells are arranged in the column direction and connected to constitute a sensing line;

the control gate electrodes of the memory cells are arranged in the column direction and connected to constitute a wordline; and

the source regions are arranged in the column direction and connected to constitute a common source line,

wherein a constant voltage (Vcc), a ground voltage (GND), a write voltage, and a turn-on voltage are applied to a select common source line, a select bitline, a select sensing line, and a select wordline which are selected in the write step, respectively; and

a ground voltage is applied to an unselect common source line, an unselect bitline, an unselect sensing line, and an unselect wordline.

37. The method of claim 36, wherein a ground voltage, a read voltage, a turn-on voltage, and a verify voltage are applied to a select common source line, a select bitline, a select sensing line, and a select wordline which are selected in the read step, respectively;

a ground voltage is applied to an unselect common source line, an unselect bitline, an unselect sensing line, and an unselect wordline.

38. The method of claim 36, wherein a ground voltage is applied to a select common source line, a select bitline, and a select sensing line which are selected in the erase step, and an erase voltage is applied to a select wordline;

and

a ground voltage is applied to an unselect common source line, an unselect bitline, an unselect sensing line, and an unselect wordline.

39. The method of claim 38, wherein the sensing line is divided into predetermined memory cell units to allow a plurality of sensing lines to correspond to respective wordlines,

in the erase step, a ground voltage is applied to a select sensing line opposite to a select wordline, and

an erase inhibit voltage is applied to an unselect sensing line opposite to the select wordline, whereby voltage levels of floating gates of memory cells rise to inhibit tunneling occurring through a tunnel insulation layer.

40. A method for fabricating a semiconductor device, comprising:

defining an active region on a semiconductor substrate;

forming a floating gate conductive layer on an entire surface of the substrate with a gate insulation layer interposed between the active region and the floating gate conductive layer;

forming a top select gate electrode on the floating gate conductive layer to cross over the active region;

patterning the floating gate conductive layer to form a floating gate on the active region;

forming a tunnel insulation layer on a sidewall of the floating gate; and

forming a sidewall select gate electrode and a control gate electrode on the tunnel insulation layer and the gate insulation layer disposed at opposite sides adjacent to the floating gate, the sidewall select gate electrode and the control gate electrode being opposite to each other.

41. The method of claim 40, wherein forming the top select gate electrode comprises:

forming spacer insulation patterns on the floating gate conductive layer, the spacer insulation patterns being opposite to each other;

forming a dielectric layer on a floating gate conductive layer between the spacer insulation patterns; and

filling a space between the spacer insulation patterns where the dielectric layer is formed with a top gate conductive layer.

42. The method of claim 41, wherein the dielectric layer includes at least one layer having a higher dielectric constant than the tunnel insulation layer.

43. The method of claim 41, wherein forming the spacer insulation patterns comprises:

forming a hard mask layer having an opening crossing over the active region on the floating gate conductive layer;

forming a spacer insulation layer on the hard mask layer; and

anisotropically etching the spacer insulation layer to form the spacer insulation pattern on a sidewall of the opening.

44. The method of claim 43, further comprising before forming the spacer insulation layer:

thermally oxidizing the floating gate conductive layer exposed to the opening to grow a sacrificial oxide pattern; and

removing the sacrificial oxide pattern to form a concave recess region.

45. The method of claim 43, wherein forming the floating gate comprises:

forming an oxide layer on the top gate conductive layer;

removing the hard mask layer; and

performing a self-align etch for the floating gate conductive layer using the oxide layer and the spacer insulation pattern as an etch mask to form the floating gate.

46. The method of claim 45, wherein forming the sidewall select gate electrode and the control gate electrode comprises:

forming a spacer conductive layer on an entire surface of the substrate; and

anisotropically etching the spacer conductive layer to form a conductive pattern on a sidewall of the spacer insulation pattern and a sidewall of the floating gate.