Current-controlled CMOS logic family

  • US 20060176094A1
  • Filed: 03/21/2006
  • Published: 08/10/2006
  • Est. Priority Date: 06/28/1999
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a first circuit block, implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, that is operable to receive and process a first signal thereby generating a second signal there from;

    a second circuit block, implemented using conventional CMOS logic wherein substantially zero static current is dissipated, that is operable to receive and process a third signal thereby generating a fourth signal there from; and

    a third circuit block, implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, that is operable to;

    receive the second signal;

    receive the fourth signal; and

    process the second signal and the fourth signal thereby generating a fifth signal there from.

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