Methods and apparatus for synchronizing data access to a local memory in a multi-processor system

• US 20060179255A1
• Filed: 02/08/2005
• Published: 08/10/2006
• Est. Priority Date: 02/08/2005
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yamazaki, Takeshi
• Granted Patent: US 7,613,886 B2
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; facilitating the data transfer into the local memory; and producing a synchronization signal indicating that the data transfer into the local memory has been completed.

Claims

1. An apparatus, comprising:

a plurality of parallel processors capable of operative communication with a shared memory;

a local memory operatively coupled to a first of the processors such that data may be transferred between the shared memory and the local memory for execution of one or more programs therein; and

a processor interface circuit coupled to the first processor and the local memory thereof and operable to separately;

(i) facilitate data transfers into and out of the local memory, and (ii) facilitate communication between the other processors and the first processor,

wherein the processor interface circuit is operable to produce a synchronization signal indicating that a data transfer into or out of the local memory has been completed.

2. The apparatus of claim 1, wherein the first processor is operable to read the transferred data from the local memory in response to the synchronization signal.

3. The apparatus of claim 1, wherein the first processor is operable to initiate a transfer of the transferred data from the local memory to the shared memory in response to the synchronization signal.

4. The apparatus of claim 1, wherein the processor interface circuit is operable to produce the synchronization signal in response to:

(i) a recover synchronization request by the first processor, and (ii) completion of the data transfer into or out of the local memory.

5. The apparatus of claim 4, wherein:

the processor interface circuit includes a channel interface circuit operable to change a processor readable value in response to a processor writable instruction; and

the recover synchronization request is issued by the first processor by writing a synchronization instruction to the channel interface circuit such that the processor readable value indicates that the synchronization request has been made.

6. The apparatus of claim 5, wherein the processor interface circuit is operable to produce the synchronization signal by writing a synchronization instruction to the channel interface circuit such that the processor readable value indicates that the data transfer into or out of the local memory has been completed.

7. The apparatus of claim 6, wherein:

the processor interface circuit includes a memory interface circuit operable to facilitate the data transfers into and out of the local memory; and

the memory interface circuit is operable to at least initiate the production of the synchronization signal by monitoring when the data transfer into or out of the local memory has been completed.

8. The apparatus of claim 6, wherein the first processor is operable to receive the synchronization signal by issuing a read instruction to the channel interface circuit and in response obtaining the processor readable value indicating that the data transfer into or out of the local memory has been completed.

9. The apparatus of claim 6, wherein the first processor is operable to at least one of:

(i) read the transferred data from the local memory, and (ii) initiate a transfer of the transferred data from the local memory to the shared memory, each in response to the synchronization signal.

10. The apparatus of claim 1, wherein the first processor is operable to issue a recover synchronization request for the synchronization signal to the processor interface circuit in response to a notification signal issued by a second one of the processors indicating that the data transfer into or out of the local memory has been initiated.

11. The apparatus of claim 10, wherein the second processor initiates the data transfer into or out of the local memory.

12. The apparatus of claim 10, wherein:

a device other than the other parallel processors initiates the data transfer into or out of the local memory; and

the device interrupts the second processor to indicate that the data transfer has been initiated.

13. The apparatus of claim 10, wherein:

the processor interface circuit includes a channel interface circuit operable to change a processor readable value in response to a processor writable instruction;

the notification signal is issued by the second processor by writing a synchronization instruction to the channel interface circuit such that the processor readable value indicates that the data transfer into or out of the local memory has been initiated; and

the first processor is operable to receive the notification signal by issuing a read instruction to the channel interface circuit, and in response obtaining the processor readable value.

14. The apparatus of claim 1, wherein the local memory is not a hardware cache memory.

15. An apparatus, comprising:

a plurality of parallel processors capable of operative communication with a shared memory;

a plurality of local memories, each being operatively coupled to a respective one of the processors such that data may be transferred between the shared memory and the local memory for execution of one or more programs therein; and

a plurality of processor interface circuits, each coupled to a respective one of the processors and the local memory thereof and each operable to separately;

(i) facilitate data transfers into and out of the local memory, and (ii) facilitate communication between the other processors and the respective processor,

wherein each processor interface circuit is operable to produce a synchronization signal indicating that a data transfer into or out of the respective local memory has been completed.

22. The apparatus of claim 15, wherein the local memory is not a hardware cache memory.

16. An apparatus, comprising:

a plurality of parallel processors capable of operative communication with a shared memory;

a local memory operatively coupled to a first of the processors such that data may be transferred between the shared memory and the local memory for execution of one or more programs therein; and

a processor interface circuit coupled to the first processor and the local memory thereof and operable to separately;

(i) facilitate data transfers into and out of the local memory, and (ii) facilitate communication between the other processors and the first processor,

wherein the processor interface circuit is operable to produce a synchronization signal indicating that a data transfer into or out of the local memory has been completed in response to;

(i) a recover synchronization request by a second one of the processors, and (ii) completion of the data transfer into or out of the local memory.

17. The apparatus of claim 16, wherein:

the processor interface circuit includes a channel interface circuit operable to change a processor readable value in response to a processor writable instruction; and

the recover synchronization request is issued by the second processor by writing a synchronization instruction to the channel interface circuit such that the processor readable value indicates that the synchronization request has been made.

18. The apparatus of claim 17, wherein:

the processor interface circuit includes a memory interface circuit operable to facilitate the data transfers into and out of the local memory; and

the memory interface circuit is operable to at least initiate the production of the synchronization signal by monitoring when the data transfer into or out of the local memory has been completed; and

the processor interface circuit is operable to produce the synchronization signal by writing a synchronization instruction to the channel interface circuit such that the processor readable value indicates that the data transfer into or out of the local memory has been completed.

19. The apparatus of claim 16, wherein the first processor is operable to at least one of:

(i) read the transferred data from the local memory, and (ii) initiate a transfer of the transferred data from the local memory to the shared memory, each in response to a notification signal from the second processor indicating that the data transfer into or out of the local memory has been completed.

20. The apparatus of claim 16, wherein:

a device other than the other parallel processors initiates the data transfer into or out of the local memory; and

the device interrupts the second processor to indicate that the data transfer has been initiated.

21. The apparatus of claim 16, further comprising:

a plurality of local memories, each being operatively coupled to a respective one of the processors such that data may be transferred between the shared memory and the local memory for execution of one or more programs therein; and

a plurality of processor interface circuits, each coupled to a respective one of the processors and the local memory thereof and each operable to separately;

(i) facilitate data transfers into and out of the local memory, and (ii) facilitate communication between the other processors and the respective processor,

wherein each of the processor interface circuits is operable to produce a synchronization signal indicating that a data transfer into or out of the respective local memory has been completed in response to;

(i) a recover synchronization request by one of the processors other than the respective processor, and (ii) completion of the data transfer into or out of the respective local memory.

23. An apparatus, comprising:

a plurality of parallel processors capable of operative communication with a shared memory;

a local memory operatively coupled to a first of the processors such that data may be transferred between the shared memory and the local memory for execution of one or more programs therein; and

a processor interface circuit coupled to the first processor and the local memory thereof and operable to separately;

(i) facilitate data transfers into and out of the local memory, and (ii) facilitate communication between the other processors and the first processor,

wherein the processor interface circuit is operable to produce a synchronization signal indicating that a plurality of data transfers into or out of the local memory have been completed.

24. The apparatus of claim 23, wherein the processor interface circuit includes a synchronization queue having a respective synchronization flag for each initiated data transfer into or out of the local memory.

25. The apparatus of claim 24, wherein the processor interface circuit is operable to change values of the respective synchronization flags in response to whether the respective data transfers into or out of the local memory have been completed.

26. The apparatus of claim 25, wherein the processor interface circuit is operable to produce the synchronization signal when the values of the respective synchronization flags indicate that the plurality of data transfers into or out of the local memory have been completed.

27. The apparatus of claim 24, wherein:

the plurality of data transfers into or out of the local memory include a first set of data transfers;

the processor interface circuit includes a storage circuit and is operable to copy a first set of the values of the respective synchronization flags associated with the first set of data transfers into the storage circuit in response to a first recover synchronization request;

the processor interface circuit is operable to change the first set of values within the storage circuit in response to respective completions of the respective data transfers into or out of the local memory; and

the processor interface circuit is operable to produce a first synchronization signal when the first set of values indicates that the first set of data transfers into or out of the local memory has been completed.

28. The apparatus of claim 27, wherein:

the plurality of data transfers includes at least a second set of data transfers;

the processor interface circuit is operable to copy a second set of the values of the synchronization flags associated with the second set of data transfers into the storage circuit in response to a second recover synchronization request;

the processor interface circuit is operable to change the second set of values within the storage circuit in response to respective completions of the respective second set of data transfers into or out of the local memory; and

the processor interface circuit is operable to produce a second synchronization signal when the second set of values indicates that the second set of data transfers into or out of the local memory has been completed.

29. The apparatus of claim 23, wherein the local memory is not a hardware cache memory.

30. An apparatus, comprising:

a plurality of parallel processors capable of operative communication with a shared memory;

a local memory operatively coupled to a first of the processors such that data may be transferred between the shared memory and the local memory for execution of one or more programs therein; and

a processor interface circuit coupled to the first processor and the local memory thereof and operable to;

(i) facilitate data transfers into and out of the local memory, (ii) facilitate communication between the other processors and the first processor, (iii) produce a synchronization signal indicating that a data transfer into or out of the local memory has been completed in response to;

(a) a recover synchronization request by at least one of the first processor and a second one of the processors, and (b) completion of the data transfer into or out of the local memory,

wherein the at least one of the first and second processors is operable to issue the recover synchronization request in response to initiation of the data transfer to the local memory by an external device in operative communication with the apparatus through a communication network.

31. The apparatus of claim 30, wherein the external device issues an interrupt signal to the second processor to indicate that the data transfer has been initiated.

32. The apparatus of claim 31, wherein the second processor is operable to produce a notification signal to the first processor to indicate that the data transfer has been initiated.

33. The apparatus of claim 30, wherein the first processor is operable to at least one of:

(i) read the transferred data from the local memory, and (ii) initiate a transfer of the transferred data from the local memory to the shared memory, each in response to the synchronization signal.

34. The apparatus of claim 30, wherein the local memory is not a hardware cache memory.

35. A method, comprising:

receiving a request from an initiating device to initiate a data transfer into or out of a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory;

facilitating the data transfer into or out of the local memory; and

producing a synchronization signal indicating that the data transfer into or out of the local memory has been completed.

36. The method of claim 35, further comprising reading the transferred data from the local memory into the first processor in response to the synchronization signal.

37. The method of claim 35, further comprising initiating a transfer of the transferred data from the local memory to the shared memory by the first processor in response to the synchronization signal.

38. The method of claim 35, further comprising producing the synchronization signal in response to:

(i) a recover synchronization request by the first processor, and (ii) completion of the data transfer into or out of the local memory.

39. The method of claim 35, further comprising:

receiving a notification signal at the first processor from a second one of the processors indicating that the data transfer into or out of the local memory has been initiated; and

issuing a recover synchronization request from the first processor for the synchronization signal such that the first processor may receive notification that the data transfer into or out of the local memory has been completed.

40. The method of claim 39, wherein initiating device is the second processor, which initiates the data transfer into or out of the local memory.

41. The method of claim 39, wherein:

the initiating device is not one of the parallel processors; and

the initiating device interrupts the second processor to indicate that the data transfer has been initiated.

42. A method, comprising:

receiving a request from an initiating device to initiate a data transfer into or out of a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory;

facilitating the data transfer into or out of the local memory;

receiving a notification signal at a second one of the plurality of processors from the initiating device indicating that the data transfer into or out of the local memory has been initiated; and

issuing a recover synchronization request from the second processor for a synchronization signal such that the second processor may receive notification that the data transfer into or out of the local memory has been completed; and

producing the synchronization signal when the data transfer into or out of the local memory has been completed.

43. The method of claim 42, further comprising at least one of:

(i) reading the transferred data from the local memory, and (ii) initiating a transfer of the transferred data from the local memory to the shared memory, each in response to a notification signal from the second processor indicating that the data transfer into or out of the local memory has been completed.

44. A method, comprising:

receiving a request from an external device to initiate a data transfer into or out of a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory, the external device being in operative communication with the parallel processors through a communication network;

receiving a notification signal at one of the first processor and a second one of the plurality of processors from the external device indicating that the data transfer into or out of the local memory has been initiated;

issuing a recover synchronization request from one of the first and second processors for a synchronization signal such that the one of the first and second processors may receive notification that the data transfer into or out of the local memory has been completed; and

producing the synchronization signal when the data transfer into or out of the local memory has been completed.

45. The method of claim 44, wherein the external device issues an interrupt signal to the second processor to indicate that the data transfer has been initiated.

46. The method of claim 45, further comprising issuing a notification signal from the second processor to the first processor to indicate that the data transfer has been initiated.

47. A method, comprising:

receiving a plurality of requests from one or more initiating devices, each request initiating a data transfer into or out of a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; and

producing a synchronization signal indicating that at least a group of the data transfers into or out of the local memory has been completed.

48. A storage medium containing a software program, the software program being operable to cause a processor to execute actions including:

receiving a request from an initiating device to initiate a data transfer into or out of a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory;

facilitating the data transfer into or out of the local memory; and

producing a synchronization signal indicating that the data transfer into or out of the local memory has been completed.

49. A storage medium containing a software program, the software program being operable to cause a processor to execute actions including:

receiving a request from an external device to initiate a data transfer into or out of a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory, the external device being in operative communication with the parallel processors through a communication network;

receiving a notification signal at one of the first processor and a second one of the plurality of processors from the external device indicating that the data transfer into or out of the local memory has been initiated;

issuing a recover synchronization request from one of the first and second processors for a synchronization signal such that the one of the first and second processors may receive notification that the data transfer into or out of the local memory has been completed; and

producing the synchronization signal when the data transfer into or out of the local memory has been completed.