Double data rate serial encoder

• US 20060179384A1
• Filed: 11/23/2005
• Published: 08/10/2006
• Est. Priority Date: 11/24/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Steele, Brian, Wiley, George Alan, Musfeldt, Curtis D.
• Granted Patent: US 7,315,265 B2
• Time in Patent Office: Days
• US Class Current: 714/741
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Claims

1. A double data rate serial encoder, comprising:

a multiplexer (mux) having a plurality of inputs;

a plurality of latches, having data inputs, coupled to the plurality of inputs of the mux;

an enabler, coupled to the latches, to enable the latches to update their data inputs; and

a counter, coupled to the mux, to select one of the plurality of inputs of the mux for output.

2. An encoder according to claim 1, wherein the mux is an N:

1 mux having N inputs and one output, wherein N is an integer power of 2.

3. An encoder according to claim 1, wherein the mux has eight inputs.

4. An encoder according to claim 1, wherein the mux provides a glitch-less output during select input transitions.

5. An encoder according to claim 1, wherein the counter provides the mux with input selection values according to a Gray code sequence.

6. An encoder according to claim 5, wherein the mux includes an output selection algorithm optimized based on a priori knowledge of the Gray code sequence.

7. An encoder according to claim 6, wherein the output selection algorithm provides a glitch-less output only during input transitions in accordance with the Gray code sequence, thereby reducing the size of the mux.

8. An encoder according to claim 7, wherein the output selection algorithm selects the mux output in accordance with the following:

Output = (sn(2) AND sn(1) AND sn(0) AND d(0)) OR (sn(2) AND sn(1) AND s(0) AND d(1)) OR (sn(2) AND s(1) AND sn(0) AND d(2)) OR (sn(2) AND s(1) AND s(0) AND d(3)) OR (s(2) AND sn(1) AND sn(0) AND d(4)) OR (s(2) AND sn(1) AND s(0) AND d(5)) OR (s(2) AND s(1) AND sn(0) AND d(6)) OR (s(2) AND s(1) AND s(0) AND d(7)) OR (sn(2) AND sn(1) AND d(1) AND d(0)) OR (sn(1) AND sn(0) AND d(4) AND d(0)) OR (sn(2) AND s(0) AND d(3) AND d(1)) OR (sn(2) AND s(1) AND d(3) AND d(2)) OR (s(2) AND sn(1) AND d(5) AND d(4)) OR (s(1) AND sn(0) AND d(6) AND d(2)) OR (s(2) AND s(0) AND d(7) AND d(5)) OR (s(2) AND s(1) AND d(7) AND d(6));

wherein s(n) represents a bit of an input selection value;

sn(n) represents the inverse of s(n); and

d(k) represents a bit of an input of the mux.

9. An encoder according to claim 1, wherein the counter transitions on either a rising or a falling edge of an input clock.

10. An encoder according to claim 9, wherein the mux outputs a bit at every edge of the input clock.

11. An encoder according to claim 1, wherein only a subset of the latches are updated while another subset of the latches are being selected for output by the mux.

12. An encoder according to claim 5, wherein the enabler enables the latches based on the input selection values generated by the counter.

13. An encoder according to claim 1, wherein the encoder receives a parallel input data and serially outputs it onto a serial communications link.

14. An encoder according to claim 1, wherein the serial communications link is a Mobile Display Digital Interface (MDDI) link.

15. A serial encoder, comprising:

means for storing a plurality of input bits;

means for generating an input selection sequence; and

means for serially outputting said plurality of input bits according to said input selection sequence.

16. A serial encoder according to claim 15, further comprising:

means for updating the plurality of input bits in said storing means.

17. A serial encoder according to claim 15, wherein said means for outputting provides a glitch-less output during input transitions in said input selection sequence.

18. A serial encoder according to claim 15, wherein said input selection sequence is a Gray code sequence.

19. A serial encoder according to claim 18, wherein said means for outputting includes an output selection algorithm optimized based on a priori knowledge of the Gray code sequence.

20. A serial encoder according to claim 19, wherein the output selection algorithm provides a glitch-less output only during input transitions in accordance with the Gray code sequence.

21. A serial encoder according to claim 17, wherein said input transitions occur on either a rising or a falling edge of an input clock.

22. A serial encoder according to claim 21, wherein said serial outputting means outputs a bit at every edge of the input clock.

23. A system, comprising:

a multiplexer (mux) having a plurality of inputs;

a plurality of latches, having data inputs, coupled to the plurality of inputs of the mux;

an enabler, coupled to the latches, to enable the latches to update their data inputs; and

a counter, coupled to the mux, to select one of the plurality of inputs of the mux for output.