Memory bus checking procedure

• US 20060187726A1
• Filed: 04/06/2006
• Published: 08/24/2006
• Est. Priority Date: 07/02/2003
• Status: Active Grant

• Current Assignee: Memory Technologies LLC (Pendrell Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Floman, Matti, Klint, Jani
• Granted Patent: US 7,275,186 B2
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines

Abstract

A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Claims

1. A method for checking a data bus between a first electronic module and a second electronic module operatively connected to the first electronic module, said method comprising:

conveying from the first electronic module to the second electronic module a first bit pattern through the data bus;

receiving in the first electronic module a second bit pattern from the second electronic module through the data bus;

the second bit pattern contains at least a part of a complementary pattern of the first bit pattern;

comparing the received second bit pattern to the first bit pattern for determining a usable bus width of the data bus based on a relationship between the first bit pattern and the complementary pattern of the first bit pattern.

3. The method of claim 1, wherein the first bit pattern has an alternate pattern of ‘

0’ and

‘

1’

.

4. The method of claim 1, wherein each bit in the received first bit pattern and the second bit pattern has a value of either ‘

0’

or ‘

1’

, and second bit pattern is complementary to the received first bit pattern such that a bit in the second bit pattern has a value different from the value of the corresponding bit in the received first bit pattern.

5. The method of claim 1, wherein the first electronic module has a maximum bus width defined by a predetermined number of bits and the received second bit pattern has a section in which the pattern is complementary to the corresponding part of the first bit pattern, said section having a further number of bits smaller than the predetermined number of bits, and wherein said comparing step determines the usable width of the data bus based on the section in the received second bit pattern.

6. The method of claim 1, further comprising:

conveying to the second electronic module a third bit pattern through the data bus, wherein the third bit pattern contains at least a part of the complementary pattern of the first bit pattern; and

receiving from the second electronic module a fourth bit pattern through the data bus, the fourth bit pattern having the predetermined relationship to the third bit pattern as received in the second electronic module.

7. The method of claim 6, further comprising

comparing the fourth bit pattern as received in the first electronic module to the third bit pattern for determining the usable bus width.

8. The method of claim 1, wherein the second electronic module comprises a memory card.

9. The method of claim 8, wherein the first electronic module has a maximum bus width and the memory card has a number of data pins, the number of data pins is equal to the number of bits conveyable on the maximum bus width.

10. The method of claim 8, wherein the first electronic module has a maximum bus width and the memory card has a number of data pins, the number of data pins is smaller than the number of bits conveyable on the maximum bus width.

11. The method of claim 8, wherein the first electronic module has a maximum bus width and the memory card has a number of data pins, the number of data pins is greater than the number of bits conveyable on the maximum bus width.

2. (canceled)

12. A software application product embedded in a computer readable medium for use in a first electronic module for checking a data bus between the first electronic module and a second electronic module, said computer readable medium having a plurality of executable codes comprising:

a code for comparing

a first bit pattern provided to the second electronic module through the data bus to

a second bit pattern received through the data bus from the second electronic module, wherein the second bit pattern is provided in response to the first bit pattern as received in the second electronic module, the second bit pattern having at least part of a complementary pattern of the received first bit pattern; and

a further code for determining a usable bus width of the data bus based on a relationship between the first bit pattern and the complementary pattern of the first bit pattern.

14. The software application product of claim 12, wherein the received first bit pattern has an alternate pattern of ‘

0’ and

‘

1’ and

the second bit pattern is complementary to the received first bit pattern.

15. The software application product of claim 12, further comprising a third code for generating the first bit pattern.

16. The software application product of claim 12, wherein the first electronic module has a maximum bus width defined by a predetermined number of bits, and the received second bit pattern has a section in which the pattern is complementary to the corresponding part of the first bit pattern, said section having a further number of bits smaller than the predetermined number of bits, and wherein the further code determines the usable width of the data bus based on the section in the received second bit pattern.

17. The software application product of claim 12, wherein the code also compares

a third bit pattern provided to the second electronic module through the data bus to

a fourth bit pattern received through the data bus from the second electronic module, wherein the third bit pattern is complementary to the first bit pattern and the fourth bit pattern is provided in response to the third bit pattern as received in the second electronic module, and the fourth bit pattern having the predetermined relationship to the received third bit pattern, so as to allow the further code to determine the usable bus width of the data bus.

13. (canceled)

18. A memory unit for use in an electronic device, the electronic device having a host electronic module for processing data and a data bus for operatively connecting the host module to the memory unit, said memory unit comprising:

a receiving mechanism for receiving a first bit pattern from the host module through the data bus; and

a conversion mechanism, responsive to the received first bit pattern, for providing a second bit pattern on the data bus, wherein the second bit pattern has at least a part of a complementary pattern of the received first bit pattern, wherein the host electronic module is adapted to compare the first bit pattern to the second bit pattern as received in the host module for determining a usable bus width of the data bus based on a predetermined relationship between the first bit pattern and the complementary pattern of the first bit pattern.

20. The memory unit of claim 18, wherein the received first bit pattern has an alternate pattern of ‘

0’ and

‘

1’ and

the second bit complement complementary to the received first bit pattern.

21. The memory unit of claim 18, wherein the data bus has a maximum bus width and the memory unit has a number of data pins for operatively connecting to the data bus, and wherein the number of data pins is smaller than number of data bits conveyable in the maximum bus width.

22. The memory unit of claim 18, wherein the data bus has a maximum bus width and the memory unit has a number of data pins for operatively connecting to the data bus, and wherein the number of data pins is equal to number of data bits conveyable in the maximum bus width.

23. The memory unit of claim 18, wherein the data bus has a maximum bus width and the memory unit has a number of data pins for operatively connecting to the data bus, and wherein the number of data pins is greater than number of data bits conveyable in the maximum bus width.

19. (canceled)

24. An electronic device having a connection mechanism to receive a memory unit, comprising:

a data processing unit;

a data bus linking the data processing unit to the memory unit; and

a program for checking the data bus, the program comprising;

a code for providing a first bit pattern to the memory unit through the data bus,

a code for requesting the memory unit to provide a second bit pattern the second bit pattern containing at least a part of a complementary pattern of the first bit pattern,

a code for comparing the first bit pattern with a second bit pattern as received through the data bus from the memory unit, and

a code for determining a usable width of the data bus based on the received second bit pattern based on a complementary relationship between the first bit pattern and the complementary pattern.

27. The electronic device of claim 24, wherein said program for checking the electronic functionality of the data bus is carried out at a boot up procedure.

28. The electronic device of claim 24, comprising a mobile phone.

29. The electronic device of claim 24, wherein said memory unit is disposed in a further electronic device.

30. The electronic device of claim 24, wherein the memory unit comprises:

a receiving mechanism for receiving the first bit pattern from the data process unit through the data bus; and

a conversion mechanism, responsive to the first bit pattern as received through the data bus, for providing the second bit pattern on the data bus.

31. The electronic device of claim 24, wherein the first bit pattern has an alternate pattern of ‘

0’ and

‘

1’

.

32. The electronic device of claim 24, wherein each bit of the received first bit pattern and the second bit patterns has a value of either ‘

0’

or ‘

1’

, and the second bit pattern is complement to the received first bit pattern.

33. The electronic device of claim 24, wherein the program further comprises

a further code for providing a third bit pattern to the memory unit through the data bus, wherein the third bit pattern is complement to the first bit pattern, so as to allow the further code to compare the third bit pattern with a fourth bit pattern received through the data bus from the memory unit, the fourth bit pattern is provided in response to the third bit pattern as received in the memory unit and the fourth bit pattern has the predetermined relationship to the received third bit pattern, and wherein the third code determines the usable width of the data bus also based on the received fourth bit pattern.

25. (canceled)

26. (canceled)