Semiconductor structures and memory device constructions

• US 20060189078A1
• Filed: 04/18/2006
• Published: 08/24/2006
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Werner Juengling
• Original Assignee: Werner Juengling
• Inventors: Juengling, Werner
• Granted Patent: US 7,547,949 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Claims

1-102. -102. (canceled)

103. A semiconductor structure comprising:

a source region formed at a top portion of a first pillar;

a drain region formed at a top portion of a second pillar;

a connecting portion of semiconductor material that connects the first and second pillars;

a gate material extending between the first and second pillars, wherein the gate material is positioned adjacent to a bottom portion of the first pillar and adjacent to a bottom portion of the second pillar; and

a channel connecting the source region and the drain region, wherein at least a portion of the channel is formed in the connecting portion of semiconductor material.

104. The semiconductor structure of claim 103, wherein the gate material is interposed between the first and second pillars.

105. The semiconductor structure of claim 103, wherein the channel is at least partially formed on an upper surface of the connecting portion of semiconductor material.

106. The semiconductor structure of claim 103, wherein the first and second pillars comprise epitaxially formed silicon.

107. The semiconductor structure of claim 103, wherein the gate material surrounds the bottom portions of the first and second pillars.

108. The semiconductor structure of claim 103, further comprising a dielectric material positioned between the channel and the gate material.

109. The semiconductor structure of claim 103, wherein the portion of semiconductor material forms a portion of a bulk substrate.

110. The semiconductor structure of claim 103, wherein the gate material comprises a material selected from the group consisting of metal, metal alloys and conductively-doped silicon.

111. The semiconductor structure of claim 103, further comprising a memory storage device connected to the drain region.

112. The semiconductor structure of claim 111, wherein the memory storage device comprises a capacitor.

113. The semiconductor structure of claim 103, further comprising a digit line connected to the source region.

114. The semiconductor structure of claim 113, further comprising a processor in communication with the digit line.

115. An integrated circuit transistor comprising:

a semiconductor structure including a pair of pillars and a connecting portion therebetween, the pillars having a bottom portion and a top portion, wherein the pillar top portions comprise heavily doped semiconductor material;

a dielectric material formed over at least a portion of the semiconductor structure;

a gate material formed on the dielectric material and positioned adjacent to the bottom portions of the pair of pillars; and

a channel extending between and forming an electrical connection between the bottom portions of the pair of pillars.

116. The integrated circuit transistor of claim 115, wherein the gate material is interposed between the pillars.

117. The integrated circuit transistor of claim 115, wherein the channel is at least partially formed on an upper surface of the connecting portion of the semiconductor structure.

118. The integrated circuit transistor of claim 115, wherein the pillars comprise an epitaxial semiconductor material.

119. The integrated circuit transistor of claim 115, wherein one of the pillar top portions comprises a source region and the other of the pillar top portions comprises a drain region.

120. The integrated circuit transistor of claim 115, wherein the gate material extends between the pillars and along side surfaces of the pillars.

121. The integrated circuit transistor of claim 115, wherein the gate material comprises a material selected from the group consisting of metal, metal alloys and conductively-doped silicon.

122. The integrated circuit transistor of claim 115, wherein the gate material is positioned adjacent to opposite sides of the pair of pillars.

123. The integrated circuit transistor of claim 115, wherein the dielectric material comprises an oxide-containing material.

124. An electronic device comprising:

a semiconductor substrate that includes a first pillar and a second pillar, wherein a source region is formed at a top portion of the first pillar, and a drain region is formed at a top portion of the second pillar;

a dielectric layer positioned over at least a portion of the substrate and at least partially over sidewall portions of the first and second pillars; and

a channel that is formed between the two pillars, and that provides an electrical connection between the source region and the drain region.

125. The electronic device of claim 124, wherein the channel is at least partially formed on an upper surface of a connecting portion of the semiconductor substrate that is located between the first pillar and the second pillar.

126. The electronic device of claim 124, wherein the pillars comprise epitaxial silicon.

127. The electronic device of claim 124, further comprising a gate material formed on the dielectric layer, the gate material extending at least along a selected sidewall of the first pillar and a selected sidewall of the second pillar, wherein the selected sidewall of the second pillar is co-linear with the selected sidewall of the first pillar.

128. The electronic device of claim 124, wherein at least a portion of the channel is on an upper surface of the semiconductor substrate between the first and second pillars.

129. The electronic device of claim 124, wherein the dielectric layer comprises an oxide material.

130. The electronic device of claim 124, further comprising:

a memory storage device electronically connected to the drain region; and

a digit line electronically connected to the source region.

131. The electronic device of claim 130, wherein the memory storage device and the gate dielectric layer form a portion of a DRAM cell.

132. The electronic device of claim 124, wherein the top portion of the first pillar is doped to a first conductivity type, and wherein a bottom portion of the first pillar is doped to a second conductivity type that is different from the first conductivity type.

133. The electronic device of claim 132, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

134. The electronic device of claim 132, wherein the first conductivity type is p-type, and the second conductivity type is n-type.