Data storewidth accelerator

  • US 20060190644A1
  • Filed: 04/08/2006
  • Published: 08/24/2006
  • Est. Priority Date: 02/03/2000
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a processor comprising a data compression engine for compressing data stored to a data storage device and for decompressing data retrieved from the data storage device;

    a programmable logic device, wherein the programmable logic device is programmed by the processor to instantiate a first interface for operatively interfacing the data storage controller to the data storage device and to instantiate a second interface for operatively interfacing the data storage controller to a host system;

    a non-volatile memory device, for storing logic code associated with the processor, the first interface and the second interface; and

    a cache memory device for temporarily storing data that is processed by or transmitted through the data storage controller;

    wherein the processor further comprises a bandwidth allocation controller for controlling access to the cache memory device by the data compression engine, the first interface and the second interface.

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