Flash memory backup system and method

• US 20060198202A1
• Filed: 12/28/2005
• Published: 09/07/2006
• Est. Priority Date: 02/18/2005
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Erez, Eran
• Granted Patent: US 8,041,879 B2
• Time in Patent Office: Days
• US Class Current: 365/185.29
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash controller transmits the page data to two flash memory devices simultaneously, such that no backup of the page data is required to be kept in the flash controller. Hence, there is no delay in writing the next page data from a host computer to the flash controller.

Claims

1. A flash memory system comprising:

(a) at least two flash memory devices, wherein at least one page buffer is allocated within each of said at least two flash memory devices; and

(b) a controller for controlling a programming of data into a first said flash memory device by steps including transmitting said data from said controller both to a page buffer of said first flash memory device and to a page buffer of a second said flash memory device.

2. The flash memory system of claim 1, wherein said controlling is implemented in software.

3. The flash memory system of claim 1, wherein said controlling is implemented in hardware.

4. The flash memory system of claim 1, wherein said controlling is implemented by a combination of software and hardware.

5. The flash memory system of claim 1, wherein said controller is operative to transmit said data substantially simultaneously to both said page buffers.

6. The flash memory system of claim 1, wherein said controller is operative to transmit said data consecutively to said page buffers.

7. The flash memory system of claim 1 further comprising:

(c) a mechanism for checking a programming failure of said programming of said data in said first flash memory device.

8. The flash memory system of claim 7, wherein said controller is operative to program said data into said second flash memory device in case of said programming failure in said first flash memory device.

9. The flash memory system of claim 8, wherein said controller is operative, subsequent to said programming of said data into said second flash memory device, to read said data from said second flash memory device.

10. The flash memory system of claim 1, wherein said flash memory devices are NAND flash memory devices.

11. A method for managing a flash memory system, the method comprising the steps of, upon the system receiving an instruction from a host to store data, obeying the instruction by:

(a) transmitting data to a first page buffer allocated within a first flash memory device of the flash memory system; and

(b) also transmitting said data to a second page buffer allocated within a second flash memory device of the flash memory system.

12. The method of claim 11, further comprising the step of:

(c) programming said data to a non-volatile memory of said first flash memory device.

13. The method of claim 12 further comprising the step of:

(d) checking a programming failure of said programming of said data in said first flash memory device.

14. The method of claim 13 further comprising the step of:

(e) programming said data to a non-volatile memory of said second flash memory device in case of said programming failure in said first flash memory device.

15. The method of claim 14 further comprising the step of:

(f) subsequent to said programming of said data into said non-volatile memory of said second flash memory device, reading said data from said non-volatile memory of said second flash memory device.

16. The method of claim 11, wherein said steps of transmitting are carried out substantially simultaneously.

17. The method of claim 11, wherein said steps of transmitting are carried out consecutively.