Reducing power consumption in a data storage system

• US 20060198225A1
• Filed: 03/04/2005
• Published: 09/07/2006
• Est. Priority Date: 03/04/2005
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Spengler, David Louis
• Granted Patent: US 7,177,222 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus and associated method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state refresh mode. A supply voltage level to the refresh load device is adjusted in relation to which of the operational and state refresh modes is employed and in relation to which of a primary alternating current derived power source or a backup battery power source is employed.

Claims

1. A method for reducing power consumption in an electronic circuit comprising a refresh load device being employed alternatively between an operational mode and a state refresh mode, the method comprising adjusting a refresh voltage level to the refresh load device in relation to which of the modes is employed.

2. The method of claim 1 wherein the adjusting step is characterized as supplying a relatively reduced refresh voltage level when the state refresh mode is employed in comparison to when the operational mode is employed.

3. The method of claim 2 wherein the adjusting step is characterized as supplying a first refresh voltage level when the operational mode is employed and alternatively supplying one of a second or third reduced refresh voltage levels when the state refresh mode is employed in relation to whether primary power or backup power is being supplied.

4. The method of claim 2 wherein the adjusting step is characterized by adjusting the refresh voltage level in relation to a mode of a dual power source arrangement associated with the refresh voltage level.

5. The method of claim 4 wherein the dual power source arrangement comprises a battery backup power source, and wherein the adjusting step is characterized by maintaining the reduced refresh voltage level as long as the state refresh mode is continuously employed in the refresh load device in conjunction with power being supplied to the refresh load device by the battery backup power source.

6. The method of claim 1 wherein the circuit comprises a dual power source arrangement comprising a battery, and wherein the adjusting step is characterized by reducing the refresh voltage level in relation to a mode of the dual power source associated with the battery powering the refresh load device.

7. A circuit comprising a power regulator that is responsive to a mode of a self refresh device in adjusting a refresh voltage level to the self refresh device when the self refresh device is in a refresh mode.

8. The circuit of claim 7 wherein the power regulator comprises a multi-state feedback control element determining an output voltage from the power regulator.

9. The circuit of claim 8 wherein the multi-state feedback control element comprises a transistor in parallel with a resistive element.

10. The circuit of claim 8 wherein the multi-state feedback control element comprises a digital potentiometer.

11. The circuit of claim 8 wherein the multi-state feedback control element comprises a digital margining device.

12. The circuit of claim 7 configured to provide a relatively reduced refresh voltage level when the self refresh device is in the refresh mode in comparison to when the self refresh device is alternatively in an operational mode.

13. The circuit of claim 12 comprising a dual source power supply, wherein the power regulator is furthermore responsive to a mode of the dual source power supply in adjusting the refresh voltage level to the self refresh device.

14. The circuit of claim 13 wherein the dual source power supply comprises a battery power source, the circuit configured to maintain the reduced refresh voltage level as long as the refresh mode is continuously employed in conjunction with power being supplied by the battery power source.

15. The circuit of claim 14 in a memory of a distributed data storage system.

21. The circuit of claim 7 configured to adjust the refresh voltage in relation to a deterministic logic matrix associating power input mode with operational mode.

22. The circuit of claim 21 configured to supply a first refresh voltage when a normal operational mode is employed and alternatively supplying one of a second or third reduced refresh voltage levels when a refresh operational mode is employed in relation to whether primary power or backup power is being supplied.

16. A data storage system, comprising:

a self-refresh memory, and

means for reducing refresh power consumption by the data storage system in relation to utilization of the memory.

17. The system of claim 16 wherein the means for reducing is characterized by associating a refresh voltage level supplied to the memory with whether the memory is in an operational mode or a refresh mode.

20. The system of claim 16 wherein the means for reducing is characterized by adjusting a refresh voltage level supplied to the memory in relation to a mode of a dual source power supply comprising a battery power source.

18. (canceled)

19. (canceled)