Protecting data transactions on an integrated circuit bus

• US 20060200641A1
• Filed: 03/04/2005
• Published: 09/07/2006
• Est. Priority Date: 03/04/2005
• Status: Active Grant

• Current Assignee: NetApp, Inc.
• Original Assignee: Network Appliance Incorporated (NetApp, Inc.)
• Inventors: Holland, Thomas C., Kalra, Pradeep K., Insley, Mark W., Snyder, Peter F.
• Granted Patent: US 7,805,629 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: H04L 1/08 by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence
• CPC Class Codes: H04L 1/1607 Details of the supervisory signal

Abstract

Provided is a method and system for protecting data transactions transmitted on an integrated circuit bus. Specifically, by transmitting data along with the complement of the data from one component to another component that are connected by the integrated circuit bus, the data and complemented data can be compared for errors. Exemplary errors include bit flips. Comparisons include logical operations, such as XOR, that determine if an error has occurred during the transmission of the data or complemented data on the integrated circuit bus.

Claims

1. A method of formatting data on an integrated circuit bus, comprising:

initiating communication between a first controller and a second controller; and

communicating protected data between the first controller and the second controller, the first and the second controller capable of communicating the protected data by using the integrated circuit bus, wherein the protected data includes a first data chunk and a second data chunk, the second data chunk being a complement of the first data chunk.

2. The method of claim 1, wherein communicating protected data further includes communicating an acknowledgement chunk after each of the first data chunk and the second data chunk.

3. The method of claim 1, further comprising:

communicating one of a read data transaction and a write data transaction during the communication of a plurality of the protected data.

4. The method of claim 1, wherein communicating the protected data further includes combining the first data chunk and the second data chunk to determine a difference between the first data chunk and the second data chunk.

5. The method for claim 4, wherein combining further includes using a logical operation.

6. The method of claim 4, further including:

detecting a difference between the first data chunk and the second data chunk.

7. The method of claim 6, wherein detecting the difference further includes voiding a transaction of the communication of a plurality of the protected data.

8. The method of claim 7, wherein each first data chunk and second data chunk is communicated until all the plurality of protected data are logically compared.

9. The method of claim 1, wherein the integrated circuit bus is an I2C bus.

10. A method of communicating data, comprising:

initiating communication between a first component and a second component; and

transmitting data and complemented data on an 12C bus from the first component to the second component, wherein the data and the complemented data are compared by the second component to determine an error.

11. The method of claim 10, wherein first component is a remote management module.

12. The method of claim 10, wherein the second component is an agent, the agent being operated by software.

13. The method of claim 10, wherein the data and the complemented data are compared by a logical operation.

14. The method of claim 10, wherein the error is a bit flip.

15. A system for protecting data communicated over an integrated circuit bus, comprising:

a first controller of a system board operating as a master for transmitting data and complemented data; and

a second controller of the system board, the second controller coupled to the first controller via the integrated circuit bus, wherein the second controller operates as a slave for receiving the data and the complemented data, the data and the complemented data being compared to detect errors.

16. The system of claim 15, wherein the integrated circuit bus is an I2C bus.

17. The system of claim 15, wherein the first controller transmits acknowledgements during read data transactions.

18. The system of claim 15, wherein the second controller transmits acknowledgements during write data transactions.

19. A system for formatting data on an integrated circuit bus, comprising:

means for initiating communication between a first controller and a second controller; and

means for communicating protected data between the first controller and the second controller, the first and the second controller capable of communicating the protected data by using the integrated circuit bus, wherein the protected data includes a first data chunk and a second data chunk, the second data chunk being a complement of the first data chunk.

20. A system of claim 19, further comprising:

means for logically comparing the first data chunk and the second data chunk to detect errors.

21. A computer readable medium having stored thereon instructions capable of being executed by a computer system, comprising:

instructions for communicating a first data chunk over an integrated circuit bus from a first controller to a second controller; and

instructions for communicating a complemented second data chunk over the integrated circuit bus from the first controller to the second controller, wherein the complemented second data chunk is compared with the first data chunk to determine whether an error occurred during the communication.