Static timing analysis and dynamic simulation for custom and ASIC designs

• US 20060200786A1
• Filed: 02/03/2006
• Published: 09/07/2006
• Est. Priority Date: 02/03/2005
• Status: Active Grant

• Current Assignee: Sage Software Incorporated (Sage Group PLC)
• Original Assignee: Sage Software Incorporated (Sage Group PLC)
• Inventors: Chang, Mau-Chung
• Granted Patent: US 7,590,953 B2
• Time in Patent Office: Days
• US Class Current: 716/108
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out failing path and identifying gate with simultaneously changing inputs, (f) Finding maximum operation frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim'"'"'s output iteratively.

Claims

1. A method for verifying timing of a circuit having a first portion with a gate-level description and a second portion with a transistor-level description, comprising:

accepting both the gate-level and transistor-level descriptions; and

using a single tool to perform timing analysis of the circuit using both the gate-level and transistor level descriptions.

2. A method according to claim 1, wherein the step of using a single tool includes obtaining timing information associated with the gate-level descriptions from a pre-characterized timing library.

3. A method according to claim 1, wherein the step of using a single tool includes decomposing circuit structures to determine timing information associated with the transistor-level descriptions.

4. A method according to claim 3, wherein the decomposing step includes:

identifying unique circuit structures associated with certain of the transistor-level descriptions; and

performing function check to obtain the associated timing information.

5. A method according to claim 1, further comprising:

using the single tool to perform timing simulation of the circuit using both the gate-level and transistor level descriptions.

6. A method according to claim 1, wherein the accepting step includes reading the descriptions from a SPICE netlist.

7. A method for verifying timing of a circuit, comprising:

accepting descriptions of the circuit;

obtaining timing information associated with the descriptions; and

using a single tool to perform both timing analysis and timing simulation of the circuit using the descriptions and timing information.

8. A method according to claim 7, wherein the step of using a single tool includes partitioning the circuit based on the descriptions.

9. A method according to claim 7, wherein the descriptions include both gate-level and transistor-level descriptions.

10. A method of verifying timing of a circuit having a portion with a transistor-level description, comprising:

automatically extracting circuit structures from the transistor-level description; and

performing timing analysis based on the extracted circuit structures.

11. A method according to claim 10, wherein the extracted circuit structures include driver-load gate, transfer gate, stage, and RLC part.

12. A method according to claim 10, wherein the circuit further includes an ASIC portion with a gate-level description, wherein the step of performing timing analysis is further based on the ASIC portion.

13. A method according to claim 10, wherein the extracting step includes:

determining a topology associated with one of the extracted circuit structures; and

comparing the topology with that of another one of the extracted circuit structures to identify a unique structure.

14. A method according to claim 13, wherein the comparing step includes searching from a top node in the topology recursively using depth first traversal.

15. A method according to claim 13, wherein the comparing step includes considering all configurations of children of a node in the topology if the node has a parallel attribute.

16. A method according to claim 13, wherein the comparing step includes considering a specific order of children of a node in the topology if the node has a series attribute.

17. A method according to claim 13, wherein the comparing step includes comparing transistor attributes in the two structures.

18. A method according to claim 13, further comprising:

determining timing information associated with the unique structure.

19. A method according to claim 18, wherein the determining step includes:

searching a path with a first portion from a triggered node to Vdd or Gnd and a second portion from the triggered node to output;

carrying out function check by propagating rise or fall at the triggered node and source or drain node along the path;

using X2Vdd, X2Gnd, Gnd2X, Vdd2X,Vdd, Gnd, rise and fall values for an affected node and propagating them further to seek more affected nodes and checking functional error until no more affected nodes are found;

disabling side paths if nodes along the side paths have unknown values; and

assigning rise or fall for each remaining input node without a known value and performing function check until one configuration is obtained without function error.

20. A method of verifying timing of a multi-phase, multi-frequency and multi-cycle circuit with level sensitive latches, comprising:

generating an event graph of nodes for paths in the circuit including at least one level-sensitive latch;

identify late arrival times for the nodes with respect to a plurality of clock phases;

identify clock phases at a destination in the circuit; and

trace back from the destination to find a failing path in the circuit.

21. A method according to claim 20, further comprising:

computing the value Q(x, node, y) for a node with respect to a source clock phase y and a destination clock phase x as Q(x,node,y)=TimingConstraint (x,y)−

LAT(node,y),

wherein TimingConstraint (x,y) is a timing constraint between source clock phase y and destination clock phase x; and

wherein LAT(node,y) is a Latest Arrival Time at the node with respect to clock phase y.

22. A method according to claim 21, wherein for any pair of y and z from the set of source clock phases:

if Q(x,node,y)<

=Q(x,node,z) for all destination clock phase x, store y for the node;

else if Q(x,node,y)>

=Q(x,node,z) for all destination clock phase x, store z for the node;

else store y and z for the node.

23. A method according to claim 20, wherein the step of finding the failing path includes tracing backward based on depth first traversal.

24. A method according to claim 21, wherein the step of finding the failing path includes determining slack between an input (in) and output (out), using the formula,

slack(in)=slack(out)+Q_in−

>

out(x)−

Q(x,out,y);

wherein Q<sub>in−

>

out</sub>(x)=Q(x,in,z)−

Delay<sub>in−

>

out,</sub>

and wherein Q(x,in,z)=TimingConstraint (x,z)−

LAT(in,z);

and wherein Q(x,out,y)=TimingConstraint(x,y)−

LAT(out,y).

25. A method of verifying timing of a circuit, comprising:

detecting a gate with simultaneously changing inputs; and

identifying a false path including the gate.

26. A method according to claim 25, further comprising:

propagating rise or fall values at nodes along the failing path and assigning values of X2Vdd, X2Gnd instead of definite value Vdd, Gnd at side inputs of the failing path;

determine simultaneously changing inputs of the gate in case the side inputs values from X2Vdd or X2Gnd to rise or fall.

27. A method of verifying timing of a circuit, comprising:

filtering out failing paths of the circuit; and

determining maximum operating frequency of the filtered circuit.

28. A method according to claim 27, further comprising:

formulating a linear programming problem for path delays satisfying the timing constraints for all of the failing paths;

identifying a first clock period that fixes timing for all of the failing paths; and

using the first clock period as an upper bound and an original clock period as a lower bound, performing a binary search to find the minimum clock period with all timing constraints being satisfied,

wherein the inverse of the minimum clock period is the maximum operating frequency.

29. A method for verifying timing of a circuit including an interconnect part with RLC inputs and RLC outputs, the method comprising:

expressing the interconnect part in terms of an admittance matrix for the RLC inputs and a voltage transfer from the RLC inputs to the RLC outputs;

pre-characterizing the admittance matrix and voltage transfer without initial condition;

integrating the interconnect with a driver part in the time domain with both the admittance matrix and the voltage transfer in the frequency domain with initial conditions.

30. A method for verifying timing of a circuit including a crosstalk victim and aggressor, comprising:

identifying a failing path including the victim;

using a first function analysis to determine whether an input of the aggressor and an input of the victim are correlated;

calculating a switching value of the aggressor input correlated to the victim input; and

using an iterative process until an input switching time for the aggressor does not change and finding a corresponding final delay of the victim.

31. A method according to claim 30, further comprising:

using a second function analysis to obtain groups of aggressors correlated to each other in the same group, but not correlated to other groups of aggressors and the victim.

32. A method according to claim 30, further comprising:

calculating a switching time of an input of a gate driving the aggressor, relative to that of the victim, by taking the difference of the delays from an input of the failing path to both the input of the gate driving the aggressor and an input of a gate driving the victim.