xDSL function ASIC processor & method of operation

• US 20060203843A1
• Filed: 01/12/2006
• Published: 09/14/2006
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Granted Patent: US 7,295,571 B2
• Time in Patent Office: Days
• US Class Current: 370/465
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An improved type of application-specific integrated circuit block (ASIC) is disclosed that is optimized for use in a communications system, and is somewhat programmble through the use of particular data objects that can specify an instruction and operand for the ASIC. The ASIC can be multi-tasking to perform multiple receive or transmit operations, two different kinds of transmit or receive operations, and operaions for mulitple ports. The ASIC generally uses an input data decoder block for decoding an input data object; a computation logic block for performing application specific computations in connection with the input data object, and an output data encoder block for encoding an output data object based on the specific computations. Using a common memory, a set of such ASICs can be arranged in a form of logical (or logical hybrid) pipeline.

Claims

1-48. -48. (canceled)

49. A communication device comprising first and second communication ports to process a first sequence of channel symbols associated with the first communication port and a second sequence of channel symbols associated with the second communication port, the first sequence of channel symbols comprising a first channel symbol and the second sequence of channel symbols comprising a second channel symbol, the communication device further comprising:

a memory to store a first object comprising a data portion indicative of the first channel symbol and comprising a parameter portion indicative of the first port, and to store a second object comprising a data portion indicative of the second channel symbol and a parameter portion indicative of the second port;

a first functional unit to process the data portion of the first object in accordance with the parameter portion of the first object; and

a second functional unit to process the data portion of the second object in accordance with the parameter portion of the second object.

50. The communication device as set forth in claim 49, further comprising:

a bus; and

a scheduler to receive the first object from the memory and to provide the first object to the first functional unit via the bus.

51. The communication device as set forth in claim 50, wherein upon completion of the first functional unit processing the data portion of the first object, the scheduler provides to the memory, for storage, the first object with its data portion processed by the first functional unit.

52. The communication device as set forth in claim 51, wherein the communication device processes the first object according to an ordered set of processing steps, wherein the first functional unit processes the first object according to a first processing step in the ordered set of processing steps, wherein after the first object has been processed by the first functional unit the first object is processed by the second functional unit according to a second processing step immediately following the first processing step in the ordered set of processing steps.

53. The communication device as set forth in claim 52, wherein the second functional unit is a programmable processor to receive the second object from the memory.

54. The communication device as set forth in claim 52, wherein the first and second channel symbols are discrete multi-tone symbols.

55. The communication device as set forth in claim 54, wherein the first functional unit processes the first object to provide QAM (quadrature-amplitude-modulation) decoding of the data portion of the first object.

56. The communication device as set forth in claim 54, wherein the first functional unit processes the first object to provide QAM (quadrature-amplitude-modulation) encoding of the data portion of the first object.

57. The communication device as set forth in claim 50, wherein the second functional unit is a programmable processor to receive the second object from the memory.

58. The communication device as set forth in claim 49, wherein the first port is configured to receive the first sequence of channel symbols and the second port is configured to receive the second sequence of channel symbols.

59. The communication device as set forth in claim 49, wherein the first port is configured to receive the first sequence of channel symbols and the second port is configured to transmit the second sequence of channel symbols.

60. The communication device as set forth in claim 49, wherein the first functional unit processes the first object to provide QAM (quadrature-amplitude-modulation) decoding of the data portion of the first object.

61. The communication device as set forth in claim 49, wherein the first functional unit processes the first object to provide QAM (quadrature-amplitude-modulation) encoding of the data portion of the first object.

62. The communication device as set forth in claim 49, wherein the data portion of the second object comprises a sequence number indicative of the channel symbol represented by the data portion of the second object.