Automated system for designing and developing field programmable gate arrays
1-20. -20. (canceled)
An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O. The mapper includes means for evaluating alternative interconnection routes between logic components within the target FPGA, and means for producing an optimized placement and routing of the logic components and interconnections on the target FPGA. The mapper also generates a low level command listing as a source file that serves as an input file for a conventional low-level FPGA programming tool. From that input file, the tool is able to generate a hardware gate-programming bitstream to be directed to the target FPGA, thereby programming the FPGA with the user-defined algorithm.
1-20. -20. (canceled)
21. A system for programming a field programmable gate array (FPGA) comprising:
means for analyzing a user-defined algorithm specified in a source code of a high level language and designed to process data vectors with one, two, or more dimensions;
means for identifying the vector processing operations of the source code;
means for mapping the vector processing operations onto logic components of an FPGA; and
means for programming the FPGA with the user-defined algorithm based on the mapping of the logic components.
- View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)