Method of fabrication of ai/ge bonding in a wafer packaging environment and a product produced therefrom

• US 20060208326A1
• Filed: 03/18/2005
• Published: 09/21/2006
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Nasiri, Steven S., Flannery, Anthony Francis Jr.
• Granted Patent: US 7,442,570 B2
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: B23K 20/023 Thermo-compression bonding
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/094 Feed-through, via
• CPC Class Codes: B81B 3/0018 Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: B81C 2203/038 Bonding techniques not provided for in B81C2203/031 - B81C2203/037
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 21/187 by direct bonding

Abstract

A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

Claims

1. A wafer structure comprising:

a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer; and

a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact;

wherein the at least one patterned substantially germanium layer is bonded to the at least one patterned aluminum layer to create a robust electrical and mechanical contact.

2. The wafer structure of claim 1 wherein the first and/or the second substrates comprise silicon substrates or multi layer of silicon substrates.

3. The wafer structure of claim 1 wherein the first and/or second substrates can be any of GaAs, InPh, SiGe substrates.

4. The wafer structure of claim 1 wherein the first and/or second substrates comprise glass substrates or glass multi layer structures.

5. The wafer structure of claim 1 wherein MEMS structures are included in the substrate.

6. The wafer structure of claim 1 wherein integrated circuits are incorporated on the substrate.

7. The wafer structure of claim 6 wherein the integrated circuit has multilayer metalization with a CMP (chemical and mechanical polishing) process of the oxide layer to allow for electrical under pass feed-through and planar metal to provide for a hermetic seal.

8. The wafer structure of claim 1 wherein contact pads are located outside the hermetic sealing ring.

9. The wafer structure of claim 1 wherein the at least one patterned substantially germanium layer and the at least one patterned aluminum layer are bonded to provide a hermetic seal.

10. The wafer structure of claim 1 wherein the at least one electrical contact comprises a plurality of electrical contacts.

11. The wafer structure of claim 1 wherein the bond is Al &

Ge eutectic composition.

12. A wafer structure comprising:

a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer and at least one via for electric feed-through; and

a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact;

wherein the at least one patterned substantially germanium layer with the at least one via is bonded to the at least one patterned aluminum to create a robust electrical and mechanical contact.

13. The wafer structure of claim 12 wherein the first and/or the second substrates comprise silicon substrates or multi layer of silicon substrates.

14. The wafer structure of claim 12 wherein the first and/or second substrates comprise glass substrates or glass multi layer structures.

15. The wafer structure of claim 12 wherein the first and/or second substrates can be any of GaAs, InPh, SiGe substrates.

16. The wafer structure of claim 12 wherein MEMS structures are included in the substrate.

17. The wafer structure of claim 12 wherein integrated circuits are incorporated on the substrate.

18. The wafer structure of claim 17 wherein the integrated circuit has multilayer metalization with a CMP (chemical and mechanical polishing) process of the oxide layer to allow for electrical under pass feed-through and planar metal to provide for a hermetic seal.

19. The wafer structure of claim 12 wherein contact pads are outside the seat ring.

20. The wafer structure of claim 12 wherein the at least one patterned substantially germanium layer and the at least one patterned aluminum layer are bonded to provide a hermetic seal.

21. The wafer structure of claim 12 wherein the at least one electrical contact comprises a plurality of electrical contacts.

22. The wafer structure of claim 12 wherein the bond is Al/Ge eutectic composition.

23. A wafer structure comprising:

a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer deposited over patterned etched standoff with precise height; and

a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact;

wherein the at least one patterned substantially germanium layer over the precise standoffs is bonded to the at least one patterned aluminum to create a robust electrical and mechanical contact, wherein a specific and precise gap is created and maintained between the first and second substrates.

24. A method for providing a wafer structure comprising the steps of:

providing a first substrate including at least one MEMS feature, the first substrate including at least one patterned substantially germanium layer; and

providing a second substrate, the second substrate including at least one patterned substantially aluminum layer and one electrical contact;

wherein the at least one patterned substantially germanium layer is bonded to the at least one patterned aluminum to create a robust electrical and mechanical contact.

25. The method of claim 24 wherein a specific temperature and time profile is used to provide the bond.

26. The method of claim 24 wherein a forming gas is used to deoxidize the contact surfaces of aluminum and germanium.

27. The method of claim 24 wherein aluminum is the standard metalization used for IC fabrication.

28. The method of claim 24 wherein the second substrate is kept below a predetermined temperature to prevent complete leaching of aluminum from the oxide surface on the second substrate.

29. The method of claim 24 wherein the bonding is performed using controlled ambient such as forming gas.

30. The method of claim 24 wherein the bonding is performed using low pressure bonding force.

31. The method of claim 24 wherein two wafers have been pre-aligned prior to bonding process.

32. The method of claim 24 wherein special cleaning solution is used to clean the oxide from both surfaces.

33. The method of claim 24 wherein the bonding surfaces are cleaned by sputter etching.

34. The method of claim 24 wherein a thin layer of TiW is used to protect the bonding surface during MEMS processing.

35. The method of claim 24 where a doped cover layer is chosen so that the nature of the electrical contact is ohmic.

36. The method of claim 24 wherein the doping of the cover layer is chosen so that the nature of the electrical contact is rectifying.

37. The method of claim 24 wherein a dielectric layer is deposited on the cover layer so that the nature of the electrical contact is insulating.

38. The method of claim 24 wherein the at least one patterned substantially germanium layer comprises approximately 500 nm of germanium and an approximate ratio mix of 97.5:

2;

0.5 of Al;

SI;

CU and is approximately 700 nm thick.