Memory tags with write only memory and reader devices and methods of use therefor

• US 20060208903A1
• Filed: 02/23/2006
• Published: 09/21/2006
• Est. Priority Date: 02/23/2005
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Rathbone, Thomas, Loh, Weng Wah, Dickin, Fraser John
• Granted Patent: US 8,610,538 B2
• Time in Patent Office: Days
• US Class Current: 340/572.800
• CPC Class Codes: G06F 21/35 communicating wirelessly
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G07G 1/009 the reader being an RFID reader

Abstract

A memory tag comprises an array of non-volatile memory, means for inductively obtaining power to enable receipt of data from and transmission of data to a reader device, a processor operable to process received data and to generate data to be transmitted; and a hash co-processor configured to apply a hash function to data applied to it. The array of non-volatile memory includes an area of write only memory. Reader devices for use with such memory tags and methods of using such memory tags are also described.

Claims

1. A memory tag, comprising:

an array of non-volatile memory;

means for inductively obtaining power to enable receipt of data from and transmission of data to a reader device;

a processor operable to process received data and to generate data to be transmitted; and

a hash co-processor configured to apply a hash function to data applied to it;

wherein the array of non-volatile memory includes an area of write only memory.

2. The memory tag according to claim 1, wherein the area of write only memory comprises memory that may be written to by a memory tag reader device having a write capability, but which may only be read by the memory tag processor.

3. The memory tag reader device according to claim 1, wherein the hash function applied by the hash co-processor is a cryptographically secure hash function.

4. The memory tag according to claim 1, comprising an area of read only memory which has stored within it a global unique identification associated with the memory tag.

5. The memory tag according to claim 1, wherein the area of write only memory has stored within it a secret key sequence.

6. The memory tag according to claim 5, wherein the area of write only memory has stored within it a second secret key sequence.

7. The memory tag according to claim 6, wherein the second key sequence is a hash digest created from the combination of a first key sequence with data stored in an area of general storage within the array of non-volatile memory.

8. The memory tag according to claim 1, wherein the means for inductively obtaining power comprises an antenna and a radio frequency coder and/or decoder.

9. The memory tag according to claim 1, wherein inductive coupling occurs between the memory tag and the memory tag reader device when the two are brought within range of each other, the range being less than 20 millimetres.

10. A memory tag reader device comprising:

means for inductively coupling with a memory tag to enable transmission of data to and receipt of data from the memory tag;

a processor operable to generate data to be transmitted and to process received data;

a hash co-processor configured to apply a hash function to data applied to it; and

an area of write only memory.

11. The memory tag reader device according to claim 10, wherein the area of write only memory may be read only by the memory tag reader device processor.

12. The memory tag reader device according to claim 10, wherein the hash function applied by the hash co-processor is a cryptographically secure hash function.

13. The memory tag reader device according to claim 10, wherein the area of write only memory has stored within it a secret key sequence.

14. The memory tag reader device according to claim 10, wherein the means for inductively coupling with a memory tag comprises an antenna and a radio frequency coder and/or decoder.

15. The memory tag reader device according to claim 10, wherein inductive coupling occurs between the memory tag reader device and the memory tag when the two are brought within range of each other, the range being less than 20 millimetres.

16. The memory tag reader device according to claim 10, wherein the hash co-processor and the area of write only memory are provided in the memory tag reader device by a memory tag acting as a co-processor, the memory tag comprising an array of non-volatile memory including an area of write only memory, means for inductively obtaining power to enable receipt of data from and transmission of data to a reader device, a processor operable to process received data and to generate data to be transmitted, and a hash co-processor configured to apply a hash function to data applied to it.

17. A method of enabling authentication of a memory tag, comprising the steps of:

writing, via an inductive link between the memory tag and a memory tag reader device with write capability, a key sequence into an area of write only memory in the memory tag; and

writing the same key sequence into an area of write only memory in at least the memory tag reader device.

18. The method of enabling authentication according to claim 17, wherein the key sequence is a series of numbers and/or letters and/or symbols known only to the entity performing the writing step.

19. The method of enabling authentication according to claim 17, comprising the further steps of:

reading, via the inductive link, a global unique identification of the memory tag; and

combining the global unique identification with a series of numbers and/or letters and/or symbols known only to the entity performing the writing step, thereby defining the key sequence.

20. The method of enabling authentication according to claim 19, wherein the series of numbers and/or letters and/or symbols known only to the entity performing the writing step is interleaved with the global unique identification.

21. A method of enabling authentication of data stored in an area of general access memory of a memory tag, comprising the steps of:

writing, via an inductive link between the memory tag and a memory tag reader device with write capability, a first key sequence into an area of write only memory in the memory tag;

writing the same first key sequence into an area of write only memory in at least the memory tag reader device;

reading, via the inductive link, the data stored in the area of general access memory;

generating a combination of the first key sequence and the data read from the area of general access memory;

generating a hash digest of the combination; and

writing the hash digest as a second key sequence into the area of write only memory in the memory tag.

22. The method of enabling authentication of data according to claim 21, wherein the first key sequence is a series of numbers and/or letters and/or symbols known only to the entity performing the writing step.