Analog to digital converter

• US 20060208935A1
• Filed: 11/14/2005
• Published: 09/21/2006
• Est. Priority Date: 03/21/2005
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Hurrell, Christopher Peter, Lyden, Colin
• Granted Patent: US 7,274,321 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03M 1/144 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

A analog to digital converter, comprising: an input for receiving an input signal to be digitised; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

Claims

1. A analog to digital converter, comprising:

an input for receiving an input signal to be digitised;

a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result;

a first residue generator for generating a first residue as a difference between the input signal and the first digital result;

a second converter core for performing a second part of the analog to digital conversion by converting the first residue;

wherein

at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search.

2. An analog to digital converter as claimed in claim 1, wherein at least one of the converter cores can determine a plurality of bits during a single trial step within that converter core.

3. An analog to digital converter as claimed in claim 1, in which the first converter core comprises a plurality of analog to digital conversion engines operating in parallel in a collaborative manner.

4. An analog to digital converter as claimed in claim 3, in which the analog to digital conversion engines comprise switched capacitor analog to digital converters, and once the first converter core has determined the first digital result the switched capacitor analog to digital converters of the first converter core are set to the first digital result such that the first converter core acts as the first residue generator.

5. An analog to digital converter as claimed in claim 1, further comprising a first amplifier for amplifying the first residue.

6. An analog to digital converter as claimed in claim 4, in which the amplifier applies a known gain.

7. An analog to digital converter as claimed in claim 5, in which the amplifier has a gain which is nominally a power of two.

8. An analog to digital converter as claimed in claim 1, in which the second conversion core comprises a plurality of analog to digital conversion engines operating in parallel in a collaborative manner.

9. An analog to digital converter as claimed in claim 1, in which a capacitive potential divider is provided in association with the second converter core so as to modify a conversion range of the second conversion core.

10. An analog to digital converter as claimed in claim 1, wherein the conversion engines include redundant bits.

11. An analog to digital converter as claimed in claim 1 wherein, for a first bit trial, only 1 bit is determined by the first converter core.

12. An analog to digital converter as claimed in claim 1, in which at least one of the converter cores comprises at least four converters, and a trial range tested by the converters is greater than and includes a range of analog values determined as a preceding least significant bit at an immediately preceding bit trial.

13. An analog to digital converter as claimed in claim 10, wherein at least some of the redundant bits are comprised of a redundant bit associated with a shift bit.

14. An analog to digital converter as claimed in claim 1, in which each conversion engine includes redundant bits and a controller associated with the conversion engine converts the result from the conversion engine into a binary word.

15. An analog to digital converter as claimed in claim 4, wherein the conversion engines of the first conversion core are connected in parallel during generation of the residue so as to reduce thermal noise.

20. An analog to digital converter as claimed in claim 1, wherein the first conversion core comprises at least three switched capacitor successive approximation conversion engines operable to determine two bits per bit trial, and wherein the first trial only trials one bit.

16. An analog to digital converter comprising:

a first stage having a plurality of conversion engines adapted to operate in a collaborative manner such that they perform a successive approximation search where two bits are determined during a trial step and where the first stage acts to form a first digital word representing a first portion of an analog signal;

an amplification stage for receiving an analog signal from the first stage representing a difference between the analog signal and the digitised first portion of the analog signal;

a second stage having a plurality of conversion engines adapted to operate in a collaborative manner such that they perform a successive approximation search where two bits are determined during a trial step and the second stage forms a second digital word; and

a combiner for combining the first and second digital words to produce an output word.

17. An analog to digital converter as claimed in claim 16, where each conversion stage comprises four conversion engines for trial range redundancy.

18. An analog to digital converter as claimed in claim 16, where each conversion engine is a switched capacitor conversion engine having redundant bits.

19. A method of converting an analog signal into a digitised value, comprising the steps of:

receiving an input signal to be digitised, using a first converter core to perform a first part of an analog to digital conversion and outputting the result of a first digital result;

forming a residue as a difference between the input signal and the first digital result;

using a second converter core to perform a second part of an analog to digital conversion by converting the first residue;

wherein

at least one of the first and second converter cores comprises at least three analog to digital conversion engines adapted to operate in a collaborative manner.

21. A method of converting an analog value into a digitised equivalent, the method comprising the steps of:

i. sampling the analog value into a plurality of first stage conversion engines;

ii. operating the first stage conversion engines in a collaborative manner to perform a successive approximation conversion where at least two bits can be determined during a single trial step;

iii. digitising a first plurality of bits to form a first digital representation, and forming a residue between the analog equivalent of the first digital representation and the analog value;

iv. amplifying the residue;

v. sampling the residue into a plurality of second stage conversion engines;

vi. operating the second stage conversion engines in a collaborative manner to perform a successive approximation conversion where at least two bits can be determined during a single trial step so as to determine a second digital representation; and

vii. using the first and second digital representations to produce a digital output value.