Software-hardware partitioning of a scheduled medium-access protocol
First Claim
1. A processing device for implementing at least a portion of a scheduled medium-access protocol in a communication system, the processing device comprising:
- a processor;
a memory coupled to the processor; and
one or more additional hardware modules;
wherein functionality of the portion of the scheduled medium-access protocol implemented in the processing device is partitioned between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;
the functionality comprising at least a scheduler and a grant generator;
wherein the scheduler is implemented in the software and the grant generator is implemented in the hardware.
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Accused Products
Abstract
A processing device, configured to implement at least a portion of a scheduled medium-access protocol (SMAP) in a communication system, comprises a processor, a memory coupled to the processor, and one or more additional hardware modules. The functionality of the portion of the SMAP implemented in the processing device is partitioned between software, stored in the memory and executable by the processor, and hardware comprising the one or more additional hardware modules. In an illustrative embodiment, the processing device comprises a head-end device of a passive optical network, and the functionality comprises at least a scheduler and a grant generator, with the scheduler being implemented in the software and the grant generator being implemented in the hardware. As a result of this software-hardware partitioning, the scheduler is able to generate updated schedules at a rate which is independent of a rate at which the grant generator generates upstream channel access grants for subscriber devices of the system, thereby improving system performance.
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Citations
22 Claims
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1. A processing device for implementing at least a portion of a scheduled medium-access protocol in a communication system, the processing device comprising:
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a processor;
a memory coupled to the processor; and
one or more additional hardware modules;
wherein functionality of the portion of the scheduled medium-access protocol implemented in the processing device is partitioned between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;
the functionality comprising at least a scheduler and a grant generator;
wherein the scheduler is implemented in the software and the grant generator is implemented in the hardware. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A processing device for implementing at least a portion of a scheduled medium-access protocol in a communication system, the processing device comprising:
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a processor;
a memory coupled to the processor; and
one or more additional hardware modules;
wherein functionality of the portion of the scheduled medium-access protocol implemented in the processing device is partitioned between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;
the functionality comprising at least a discovery element and a grant processor;
wherein the discovery element is implemented in the software and the grant processor is implemented in the hardware.
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20. A method of implementing at least a portion of a scheduled medium-access protocol in a processing device of a communication system, the processing device comprising a processor, a memory coupled to the processor, and one or more additional hardware modules, the method comprising:
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partitioning functionality of the portion of the scheduled medium-access protocol implemented in the processing device between software stored in the memory and executable by the processor and hardware comprising the one or more additional hardware modules;
the functionality comprising at least a scheduler and a grant generator;
wherein the scheduler is implemented in the software and the grant generator is implemented in the hardware. - View Dependent Claims (21, 22)
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Specification