CMOS image sensor having wide dynamic range

• US 20060219866A1
• Filed: 03/28/2006
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Egawa, Yoshitaka, Ohsawa, Shinji
• Granted Patent: US 7,733,402 B2
• Time in Patent Office: Days
• US Class Current: 250/208.100
• CPC Class Codes: H04N 23/72 Combination of two or more compensation controls
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/589 with different integration times, e.g. short and long exposures
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A solid-state image sensing device includes a pixel unit, analog-to-digital converter, controller, and adder. In the pixel unit, cells are two-dimensionally arranged on a semiconductor substrate. An output analog signal from the pixel unit is converted into a digital signal by the analog-to-digital converter and output. The controller controls the pixel unit and analog-to-digital converter, and causes the analog-to-digital converter to digitize a plurality of analog signals different in storage time in the pixel unit during the storage period of the electric charge of one frame. The adder adds digital signals corresponding to the analog signals different in storage time and output from the analog-to-digital converter.

Claims

1. A solid-state image sensing device comprising:

a pixel unit in which cells each including photoelectric converting means for storing an electric charge obtained by photoelectrically converting incident light, reading means for reading out the electric charge stored in the photoelectric converting means to a detection node, amplifying means for amplifying the electric charge read out to the detection node and outputting the amplified electric charge, and resetting means for resetting the detection node are two-dimensionally arranged on a semiconductor substrate;

an analog-to-digital converter configured to convert an output analog signal from the amplifying means into a digital signal, and output the digital signal;

a controller configured to control the pixel unit and the analog-to-digital converter, and cause the analog-to-digital converter to digitize a plurality of analog signals different in storage time during a storage period of an electric charge of one frame; and

an adder configured to add digital signals corresponding to said plurality of analog signals different in storage time and output from the analog-to-digital converter.

2. A device according to claim 1, further comprising load transistors for a source follower circuit, current paths of the load transistors being connected between vertical signal lines of the pixel unit and a ground point, and a bias generator which applies a bias voltage to a gate of the load transistor.

3. A device according to claim 2, further comprising a reference waveform generator which generates a reference waveform for digitization, and supplies the reference waveform to the analog-to-digital converter.

4. A device according to claim 3, wherein the reference waveform for digitization generated by the reference waveform generator includes a first triangular wave and a second triangular wave to execute digitization twice in one horizontal scanning period.

5. A device according to claim 2, further comprising a noise canceller which is placed between the pixel unit and the analog-to-digital converter, removes noise from an analog signal corresponding to the electric charge generated by the photoelectric converting means, and supplies the analog signal to the analog-to-digital converter.

6. A device according to claim 5, further comprising a latch circuit which latches an output digital signal from the analog-to-digital converter.

7. A device according to claim 6, further comprising a shift register which sequentially transfers and reads out the digital signal latched by the latch circuit.

8. A device according to claim 1, wherein the adder comprises a line memory which receives one of digital signals obtained by digitizing a plurality of analog signals different in storage time in the photoelectric converting means by the analog-to-digital converter, and adds a delayed digital signal output from the line memory and a digital signal not delayed by the line memory.

9. A device according to claim 1, further comprising a circuit configured to add digital signals corresponding to an analog long-storage-time signal and an analog short-storage-time signal individually read out from the pixel unit, digitized by the analog-to-digital converter, and read out to a pair of different vertical lines.

10. A device according to claim 1, further comprising a wide dynamic range mixer circuit configured to amplify a digital signal corresponding to an analog short-storage-time signal read out from the pixel unit and digitized by the analog-to-digital converter, add the amplified digital signal and a digital signal corresponding to an analog long-storage-time signal to make the number of bits larger than the number of bits of the analog-to-digital converter, and output a sum signal.

11. A device according to claim 10, further comprising a signal compressor configured to highly compress the output signal from the wide dynamic range mixer circuit into a short-storage-time signal by a gamma table or segmented compression conversion.

12. A device according to claim 1, further comprising a first vertical register for controlling a long storage time and a second vertical register for controlling a short storage time, both of which are used to control a storage time of the pixel unit.

13. A device according to claim 1, further comprising a voltage controller which varies a readout voltage from the reading means in an operation period of one frame.

14. A device according to claim 1, further comprising a voltage controller which varies an applied voltage of the resetting means in an operation period of one frame.

15. A device according to claim 1, further comprising a circuit which pairs a long-storage-time signal and a short-storage-time signal of different vertical lines in the pixel unit, separately reads out and A/D-converts the signals, and adds A/D-converted output signals.

16. A device according to claim 1, wherein the photoelectric converting means comprises a photodiode having a grounded anode, the reading means comprises a read transistor having a current path one end of which is connected to a cathode of the photodiode, and having a gate to which a read pulse is supplied, the amplifying means comprises an amplifying transistor having a gate connected to the other end of the current path of the read transistor, and having a current path one end of which is connected to a vertical signal line, the resetting means comprises a reset transistor having a current path one end of which is connected to a power supply, and the other end of which is connected to the gate of the amplifying transistor, and having a gate to which a reset pulse is supplied, and the detection node comprises a connecting node which connects the gate of the amplifying transistor, the other end of the current path of the read transistor, and the other end of the current path of the reset transistor.

17. A device according to claim 16, further comprising a row select transistor having a current path one end of which is connected to the power supply, and the other end of which is connected to the other end of the current path of the amplifying transistor, and having a gate to which an address pulse is supplied.