Non-volatile multi-level semiconductor flash memory device and method of driving same

• US 20060221685A1
• Filed: 05/05/2006
• Published: 10/05/2006
• Est. Priority Date: 07/10/1996
• Status: Active Grant

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Yamada, Naoki, Miyazawa, Kazuyuki, Tsujikawa, Tetsuya, Sato, Hiroshi
• Granted Patent: US 7,257,026 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.

Claims

1. A nonvolatile memory comprising:

a plurality of memory cells; and

a plurality of word lines, each of which couples to corresponding ones of said memory cells,

wherein said nonvolatile memory is capable of receiving a plurality of commands which includes a write command accompanied with write address information,

wherein, when said nonvolatile memory receives said write command accompanied with first address information as said write address information and first data, said nonvolatile memory selects a first word line according to said first address information, and stores said first data to said memory cells coupled to said first word line,

wherein, after storing said first data and without erasing said first data stored in said memory cells when said nonvolatile memory receives said write command accompanied with second address information as said write address information and second data, said nonvolatile memory also selects said first word line according to said second address information, further modifying a storing state in said memory cells coupled to said first word line in response to said second data,

wherein, after storing said first data, each of said memory cells coupled to said first word line has one state of a first state and a second state, said first and second states being discriminated by one threshold, and

wherein, after modification of said storing state in said memory cells in response to said second data, each of said memory cells coupled to said first word line has one state of a third state, a fourth state, a fifth state and a sixth state, said third, fourth, fifth and sixth states being discriminated by three thresholds.

2. A nonvolatile memory according to claim 1, wherein a memory cell coupled to said first word line has one state of said first state and said second state according to data of said first data to be stored,

wherein said memory cell coupled to said first word line has one state of said third state and said fourth state according to data of said second data to be stored, when said memory cell has said first state after storing data of said first data to be stored, and

wherein said memory cell coupled to said first word line has one state of said fifth state or said sixth state according to data of said second data to be stored, when said memory cell has said second state after storing data of said first data to be stored.

3. A nonvolatile memory according to claim 2, wherein said commands further include a read command

accompanied with read address information,

wherein, when said nonvolatile memory receives said read command accompanied with said first address information as said read address information, said nonvolatile memory selects said first word line according to said first address information, and outputs said first data stored in said memory cells coupled to said first word line, and

wherein, when said nonvolatile memory receives said read command accompanied with said second address information as said read address information, said nonvolatile memory selects said first word line according to said second address information, and outputs said second data stored in said memory cells coupled to said first word line.

4. A nonvolatile memory according to claim 1, wherein said first state is near to said third state, and

wherein said second state is near to said fifth state.

5. A nonvolatile memory according to claim 4, wherein said first state is an erased state, and wherein all of said memory cells coupled to said first word line are modified from said storing state into said first state, before receiving said write command accompanied with said first address information.

6. A nonvolatile memory according to claim 1, wherein said one threshold for discriminating between said first state and said second state is near to one of said three thresholds for discriminating said third, said fourth, said fifth and said sixth states.

7. A nonvolatile memory according to claim 6, wherein said one of three thresholds is for discriminating between said third state and said sixth state.

8. A nonvolatile memory according to claim 7, wherein said fourth state is arranged to a lowest voltage level,

wherein said fifth state is arranged to a highest voltage level,

wherein said third state is arranged to a higher voltage level than said fourth state, and

wherein said sixth state is arranged between a voltage level of said third state and a voltage level of said fifth state.