Decoding circuit for non-binary groups of memory line drivers

• US 20060221702A1
• Filed: 06/07/2005
• Published: 10/05/2006
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G., Petti, Christopher J.
• Granted Patent: US 7,272,052 B2
• Time in Patent Office: Days
• US Class Current: 365/185.230
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.

Claims

1. An integrated circuit comprising:

a memory array comprising a plurality of array lines;

a number of array line driver circuits coupled with the plurality of array lines, wherein the number is other than an integral power of two; and

control circuitry configured to select one of the array line driver circuits.

2. The integrated circuit of claim 1, wherein the number comprises six.

3. The integrated circuit of claim 1, wherein the control circuitry is operative to leave holes in a decode map.

4. The integrated circuit of claim 1, wherein the control circuitry comprises a binary decoder portion, and a pre-binary-decoder portion operative to perform a non-binary arithmetic operation.

5. The integrated circuit of claim 4, wherein the non-binary arithmetic operation comprises a modulo three remainder operation.

6. The integrated circuit of claim 1, wherein the plurality of array lines comprise word lines, and wherein the plurality of array line driver circuits comprise word line driver circuits.

7. The integrated circuit of claim 1 further comprising:

a binary decoder operative to select a group of array lines; and

circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder.

8. The integrated circuit of claim 7, wherein the non-binary arithmetic operation comprises a divide-by-three operation.

9. The integrated circuit of claim 1, wherein the memory array comprises a three-dimensional memory array comprising a monolithic semiconductor integrated circuit incorporating more than one memory plane formed above and below each other and above a semiconductor substrate, and wherein the plurality of array line driver circuits and the decoder circuit are disposed within the semiconductor substrate under the three-dimensional memory array.

10. An integrated circuit comprising:

a memory array comprising a plurality of array lines;

a non-binary number of array line driver circuits coupled with the plurality of array lines; and

a decoder circuit coupled with the non-binary number of array line driver circuits, the decoder circuit comprising;

a binary decoder; and

circuitry operative to perform a non-binary arithmetic operation,

wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder.

11. The integrated circuit of claim 10, wherein the number comprises six.

12. The integrated circuit of claim 10, wherein the non-binary arithmetic operation comprises a modulo three remainder operation.

13. The integrated circuit of claim 10, wherein the plurality of array lines comprise word lines, and wherein the plurality of array line driver circuits comprise word line driver circuits.

14. The integrated circuit of claim 10 further comprising:

a second binary decoder, the second binary decoder operative to select a group of array lines; and

second circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation of the second circuitry is provided as input to the binary decoder.

15. The integrated circuit of claim 14, wherein the non-binary arithmetic operation performed by the second binary decoder comprises a divide-by-three operation.

16. The integrated circuit of claim 10, wherein the memory array comprises a three-dimensional memory array comprising a monolithic semiconductor integrated circuit incorporating more than one memory plane formed above and below each other and above a semiconductor substrate, wherein the plurality of array line driver circuits and the decoder circuit are disposed within the semiconductor substrate under the three-dimensional memory array.

17. An integrated circuit comprising:

a binary decoder; and

circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder.

18. The integrated circuit of claim 17, wherein the binary decoder comprises a post-decode portion comprising a non-binary multiplicity.

19. The integrated circuit of claim 17, wherein the binary decoder is operative to select one of a non-binary number of array line driver circuits coupled with plurality of array lines of a memory array.

20. The integrated circuit of claim 17, wherein the non-binary arithmetic operation comprises a modulo three remainder operation.

21. An integrated circuit comprising:

a memory array comprising a plurality of array lines;

a plurality of groups of array line driver circuits coupled with the plurality of array lines;

a number of array line driver circuits in at least one of the plurality of groups of array line driver circuits, wherein the number is other than an integral power of two; and

control circuitry configured to select one of the array line driver circuits.

22. The integrated circuit of claim 21, wherein the array line driver circuits in at least one of the plurality of groups share a control input signal provided by the control circuitry.

23. The integrated circuit of claim 21, wherein the memory array comprises a plurality of sub arrays, and wherein at least one of the plurality of the groups of array line driver circuits support one or two sub arrays of memory cells