In-plane switching mode liquid crystal display device

• US 20060227276A1
• Filed: 04/10/2006
• Published: 10/12/2006
• Est. Priority Date: 04/11/2005
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Son, Hyeon Ho
• Granted Patent: US 7,599,033 B2
• Time in Patent Office: Days
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136218 Shield electrodes

Abstract

An IPS mode LCD device includes first and second substrates facing each other, gate and data lines on the first substrate and crossing each other to define a plurality of unit pixel regions, first and second electrode patterns formed in an island shape at a pre-determined interval therebetween and overlapped with sides of the data line, a plurality of common electrodes formed in the unit pixel regions, each of the common electrodes having outermost common electrodes partially overlapped with the first and second electrode patterns, a pixel electrode alternately provided with the common electrodes within the pixel unit region, and a liquid crystal layer formed between the first and second substrates.

Claims

1. An IPS (In-Plane Switching) mode LCD device, comprising:

first and second substrates facing each other;

gate and data lines on the first substrate and crossing each other to define a plurality of unit pixel regions;

first and second electrode patterns formed in an island shape at a predetermined interval therebetween and overlapped with sides of the data line;

a plurality of common electrodes formed in the unit pixel regions, each of the common electrodes having outermost common electrodes partially overlapped with the first and second electrode patterns;

a pixel electrode alternately provided with the common electrodes within the pixel unit region; and

a liquid crystal layer formed between the first and second substrates.

2. The device according to claim 1, wherein the first and second electrode patterns are formed in the same layer as the gate line.

3. The device according to claim 1, wherein the first and second electrode patterns are formed in the same layer as the pixel electrode.

4. The device according to claim 1, wherein the common electrodes and the pixel electrode include a transparent material.

5. The device according to claim 1, further comprising a common line extending across the unit pixel region parallel to the gate line.

6. The device according to claim 5, wherein the common line is electrically connected with the common electrode.

7. The device according to claim 5, wherein the common line is formed in the same layer as the gate line.

8. The device according to claim 1, further comprising a thin film transistor formed adjacent to the crossing of the gate and data lines, wherein a thin film transistor includes a gate electrode protruding from the gate line, a source electrode protruding from the data line, and a drain electrode formed at a predetermined interval from the source electrode.

9. The device according to claim 8, wherein the drain electrode is electrically connected with the pixel electrode.

10. The device according to claim 1, further comprising a gate insulating layer between the gate line and the data line.

11. The device according to claim 1, further comprising a passivation layer between the data line and the pixel electrode.

12. The device according to claim 11, wherein the passivation layer includes an organic insulating material.

13. An IPS (In-Plane Switching) mode LCD device comprising:

first and second substrates facing each other;

gate and data lines on the first substrate and crossing each other to define a plurality of unit pixel regions;

a thin film transistor (TFT) formed adjacent to the crossing of the gate and data lines, the TFT includes a gate electrode protruding from the gate line, a source electrode protruding from the data line, and a drain electrode formed at a predetermined interval from the source electrode;

first and second electrode patterns formed in an island shape at a predetermined interval therebetween and overlapped with sides of the data line;

a common line formed extending across the pixel region parallel to the gate line;

a plurality of common electrodes electrically connected with the common line in the unit pixel region, each of the common electrodes having outermost common electrodes partially overlapped with the first and second electrode patterns;

a pixel electrode alternately provided with the common electrodes within the unit pixel region and electrically connected with the drain electrode of the pixel region;

a gate insulating layer formed between the data line, the gate line, the common line, first electrode pattern and the second electrode pattern;

a passivation layer formed between the data line, the common electrode and the pixel electrode; and

a liquid crystal layer formed between the first and second substrates.

14. The device according to claim 13, wherein the passivation layer includes an organic insulating material.

15. The device according to claim 13, wherein the gate line, the common line, the first electrode pattern and the second electrode pattern are formed in the same layer.

16. The device according to claim 13, wherein the pixel electrode and the common electrodes are formed in the same layer.

17. The device according to claim 16, wherein the pixel electrode and the common electrode include a transparent material.

18. An IPS (In-Plane Switching) mode LCD device, comprising:

first and second substrates facing each other;

gate and data lines on the first substrate and crossing each other to define a plurality of unit pixel regions;

a thin film transistor (TFT) formed adjacent to the crossing of the gate and data lines, the TFT including a gate electrode protruding from the gate line, a source electrode protruding from the data line, and a drain electrode formed at a predetermined interval from the source electrode;

first and second electrode patterns formed in an island shape at a predetermined interval therebetween and overlapped with sides of the data line;

a common line formed extending across the pixel region parallel to the gate line;

a plurality of common electrodes electrically connected with the common line in the pixel region, each of the common electrodes having outermost common electrodes partially overlapped with the first and second electrode patterns;

a pixel electrode alternately provided with the common electrodes in the pixel region and electrically connected with the drain electrode of the pixel region;

a gate insulating layer formed between the data line and the gate line, the common line and the common electrode;

a passivation layer formed between the data line and the first electrode pattern, the second electrode pattern, and the pixel electrode; and

a liquid crystal layer formed between the first and second substrates.

19. The device according to claim 18, wherein the gate line, the common line, and the common electrode are formed in the same layer.

20. The device according to claim 18, wherein the first and second electrode patterns are formed in the same layer as the pixel electrode.

21. The device according to claim 20, wherein the first and second electrode patterns and the pixel electrode include a transparent material.

22. The device according to claim 18, wherein the passivation layer includes an organic insulating material.