Systems and methods for CPU repair

• US 20060230230A1
• Filed: 02/17/2006
• Published: 10/12/2006
• Est. Priority Date: 02/18/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kuntz, Guy, Sedmak, Michael, Pomaranski, Ken, Barlow, Jeff, Brauch, Jeff, Joyal, Lacey, Hack, Stephen, Calkin, Howard, Gratias, Raymond
• Granted Patent: US 8,667,324 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/121 using replacement algorithms

Abstract

In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.

Claims

1. A method for ranking CPU cache element quality comprising the steps of:

logging cache error information following an error in a cache element; and

assigning a quality rank to said cache element corresponding to a number of errors occurring in said cache element over a predetermined time period.

2. The method of claim 1, wherein said cache error information includes which element said error occurred and when said error occurred.

3. The method of claim 1, further comprising the step of:

storing said quality rank into a non-volatile memory.

4. The method of claim 1, further comprising the steps of:

updating a cache error history database with said logged cache error information; and

evaluating said cache error history database to determine said quality rank.

5. A method for prolonging processor life comprising the steps of:

determining that an allocated cache element is faulty based on a quality rank of said allocated cache element; and

swapping in a non-allocated cache element for said faulty allocated cache element.

6. The method of claim 5, further comprising the steps of:

logging cache error information following an error in a cache element;

updating a cache error history database with said logged cache error information;

evaluating said cache error history database to determine said quality rank; and

assigning said quality rank to said cache element corresponding to a total number of errors occurring in said cache element over a predetermined time period.

7. The method of claim 5, further comprising the step of:

determining whether said non-allocated cache element is available if said allocated cache element is determined to be faulty.

8. The method of claim 7, further comprising the step of:

de-allocating said processor if said non-allocated cache element is not available.

9. The method of claim 8, further comprising the step of:

swapping in a non-allocated processor for said de-allocated processor.

10. The method of claim 5, further comprising the step of:

reporting actions taken and updating cache configuration on a memory device.

11. A CPU cache element management system comprising:

at least one processor having at least one allocated cache element and at least one non-allocated cache element;

a cache management logic operable to assign a quality rank to said allocated cache element corresponding to a total number of errors occurring in said cache element over a predetermined time period.

12. The CPU cache element management system of claim 11, wherein said cache management logic is further operable to swap in said non-allocated cache element for said allocated cache element if said allocated cache element is deemed faulty based on said quality rank.

13. The CPU cache element management system of claim 12, wherein said cache management logic is further operable to monitor cache errors and record cache error information in a memory.

14. The CPU cache element management system of claim 11, wherein said cache management logic is further operable to determine whether said non-allocated cache element is available if said allocated cache element is deemed faulty.

15. The CPU cache management system of claim 14, wherein said cache management logic is further operable to de-allocate said processor if said non-allocated cache element is not available.

16. The CPU cache management system of claim 15, wherein said cache management logic is further operable to swap in a non-allocated processor for said de-allocated processor.

17. The CPU cache management system of claim 11, wherein said cache management logic is further operable to report actions taken and update cache configuration on a memory device.

18. The CPU cache management system of claim 13, wherein said cache management logic is further operable to log cache error information following an error in a cache element, to update a cache error history database with said logged cache error information, to evaluate said cache error history database to determine said quality rank.

19. A computer system comprising:

at least one processor having at least one allocated cache element and at least one non-allocated cache element; and

a cache management logic operable to assign a quality rank to said allocated cache element corresponding to a total number of errors occurring in said cache element over a predetermined time period.

20. The computer system of claim 19, wherein said cache management logic is further operable to swap in said non-allocated cache element for said allocated cache element if said allocated cache element is deemed faulty based on said quality rank.

21. The computer system of claim 20, wherein said cache management logic is further operable to monitor cache errors and record cache error information in a memory.

22. The computer system of claim 19, wherein said cache management logic is further operable to determine whether said non-allocated cache element is available if said allocated cache element is deemed faulty.

23. The computer system of claim 22, wherein said cache management logic is further operable to de-allocate said processor if said non-allocated cache element is not available.

24. The computer system of claim 23, wherein said cache management logic is further operable to swap in a non-allocated processor for said de-allocated processor.

25. The computer system of claim 19, wherein said cache management logic is further operable to report actions taken and update cache configuration on a memory device.

26. The computer system of claim 21, wherein said cache management logic is further operable to log cache error information following an error in a cache element, to update a cache error history database with said logged cache error information, to evaluate said cache error history database to determine said quality rank.

27. A method for managing a computer system having an operating system comprising the steps of:

monitoring an allocated cache element on a processor for an error;

logging cache error information following said error in said allocated cache element;

updating a cache error history database with said logged cache error information;

evaluating said cache error history database to determine a quality rank for said allocated cache element;

assigning said quality rank to said allocated cache element corresponding to a total number of errors occurring in said allocated cache element over a predetermined time period; and

determining whether said allocated cache element is faulty based on said quality rank of said allocated cache element.

28. The method of claim 27, further comprising the steps of:

swapping in a non-allocated cache element if said non-allocated cache element is available and said allocated cache element is faulty while said operating system is running; and

updating cache configuration in a memory.