Programmable pipeline array

• US 20060233006A1
• Filed: 03/28/2006
• Published: 10/19/2006
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Wave Semiconductor, Inc.
• Original Assignee: Theseus Research, Inc.
• Inventors: Fant, Karl M.
• Granted Patent: US 7,478,222 B2
• Time in Patent Office: Days
• US Class Current: 365/1
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.

Claims

1. An apparatus comprising:

an array of programmable data-processing cells configured as a plurality of cross-connected pipelines.

2. An apparatus including a plurality of cells, each of the plurality of cells capable of performing a plurality of data-processing functions selectable by a presented instruction, the apparatus comprising:

a first set of cells, the first set including (a) an input cell, (b) an output cell, and (c) a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell; and

a second set of cells, the second set including (a) an input cell, (b) an output cell, and (c) a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell;

wherein

a data output of a cell of the first series, other than the output cell, connects to a data input of a cell of the second series; and

a data output of a cell of the second series, other than the output cell, connects to a data input of a cell of the first series.

3. The apparatus of claim 2 further comprising memory presenting to each of a plurality of interior cells an instruction selecting a function of the interior cell.

4. The apparatus of claim 2 further comprising:

memory presenting to a cell of the first set an instruction steering a data output of the cell of the first set to a cell of the second set; and

memory presenting to a cell of the second set an instruction steering a data output of the cell of the second set to a cell of the first set.

5. The apparatus of claim 2 further comprising:

memory presenting to a cell of the first set an instruction selecting, as an input, data from a cell of the second set; and

memory presenting to a cell of the second set an instruction selecting, as an input, data from a cell of the first set.

6. The apparatus of claim 2 further comprising:

memory presenting configuration instructions to a plurality of cells in response to a configuration code.

7. The apparatus of claim 6 wherein:

data presented in tandem to input cells advances in tandem through ranks of the sets as processed data.

8. The apparatus of claim 7 wherein a configuration code advances to memory associated with a rank of the sets in tandem with data advancing to the rank.

9. The apparatus of claim 6 wherein a first rank of cells is configured to perform first functions on first data while, simultaneously, a second rank of cells is configured to perform a second function on second data.

10. The apparatus of claim 2 further comprising at least a third set of cells, the third set including (a) an input cell, (b) an output cell, and (c) a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell;

wherein;

a data output of a cell, other than the output cell, of the third set connects to a data input of a cell of the second set; and

a data output of a cell, other than the output cell, of the second set connects to a data input of a cell of the second set.

11. A data processing method comprising:

providing a first set of cells, the first set including (a) an input cell, (b) an output cell, and (c) a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell;

providing a second set of cells, the second set including (a) an input cell, (b) an output cell, and (c) a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell;

providing memory capable of presenting configuration instructions to a plurality of cells in response to a configuration code;

presenting first data to the input cells;

presenting a first configuration code to memory associated with the input cells;

advancing the first data in tandem through ranks of the sets of cells as first processed data; and

advancing the configuration code to memory associated with a rank of the sets of cells in tandem with the first processed data advancing to the rank.

12. The method of claim 11 wherein a step of advancing the data in tandem through ranks of the sets of cells includes a step of steering data from a cell of one set to a cell of another set.

13. The method of claim 11 wherein a step of advancing the data in tandem through ranks of the sets of cells includes a step of selecting, as an input to a cell of a set, data from a cell of another.

14. The method of claim 11 further including steps of:

presenting second data to the input cells;

presenting a second configuration code to memory associated with the input cells;

advancing the second data in tandem through ranks of the sets of cells as processed data; and

advancing the second configuration code to memory associated with a rank of the sets of cells in tandem with the processed second data advancing to the rank.

15. The method of claim 11 wherein the first processed data has advanced to a first rank while the second processed data has advanced to a second rank.

16. The method of claim 11 further including a step of providing at least a third set of cells, the third set including (a) an input cell, (b) an output cell, and (c) a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell;

wherein;

a data output of a cell, other than the output cell, of the third series connects to a data input of a cell of the second series; and

a data output of a cell, other than the output cell, of the second series connects to a data input of a cell of the second series.

17. An apparatus comprising:

a plurality of pipeline means for programmably processing data as a series of wavefronts through a plurality of ranks, and

memory means for providing instructions to the ranks of the pipeline means.