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Soft error correction method, memory control apparatus and memory system

  • US 20060236208A1
  • Filed: 08/05/2005
  • Published: 10/19/2006
  • Est. Priority Date: 03/17/2005
  • Status: Active Grant
First Claim
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1. A soft error correction method for a memory system having n memory access controllers that are configured to access n memories for storing byte-sliced data in cycle synchronism, and a system controller that is configured to receive a memory access from an arbitrary one of m MPUs and to issue a memory address with respect to the n memory access controllers, where m and n are integers greater than or equal to two, comprising:

  • when a correctable error is detected in data read from one of the memories, holding an error address where the error was detected within a corresponding one of the memory access controllers, and making an error notification with respect to the system controller from the corresponding one of the memory access controllers; and

    responsive to the error notification, controlling the one of the memory access controllers holding the error address from the system controller without intervention from the MPUs, reading the data from the error address of the corresponding one of the memories, correcting the error and rewriting corrected data to the error address.

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