Ultra thin body fully-depleted SOI MOSFETs

• US 20060237791A1
• Filed: 06/23/2006
• Published: 10/26/2006
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Min, Doris, Bruce B., Ren, Zhibin, Solomon, Paul M., Ieong, Meikei
• Granted Patent: US 7,459,752 B2
• Time in Patent Office: Days
• US Class Current: 257/348
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of creating ultra thin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.

Claims

1. A silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) comprising:

a silicon-on-insulator (SOI) substrate having a SOI layer in which a first portion thereof has a thickness of less than about 20 nm;

a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having said thickness; and

source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to said first portion, said second portion of the SOI layer is thicker than the first portion.

2. The SOI MOSFET of claim 1 further comprising an outer insulating spacer about the gate.

3. The SOI MOSFET of claim 1 wherein said gate conductor comprises doped polysilicon.

4. The SOI MOSFET of claim 1 further comprising an undoped or counter-doped device channel beneath said gate, wherein said SOI layer thickness decreases with short channel lengths.

5. The SOI MOSFET of claim 1 further comprising a doped device channel beneath said gate, wherein said SOI layer thickness increases with short channel lengths.

6. A semiconductor structure comprising a plurality of fully-depleted metal oxide semiconductor field effect transistors (MOSFETS) located on a top Si-containing layer of a silicon-on-insulator substrate, wherein said Si-containing layer under each MOSFET has a thickness that varies depending upon a gate length of each MOSFET.

7. The semiconductor structure of claim 6 wherein each MOSFET comprises a device channel in said top Si-containing layer having a vertical thickness of less than about 20 nm;

a gate including a gate dielectric and a gate electrode located atop the device channel; and

source and drain diffusion regions located in said top Si-containing layer that is adjacent to said device channel, said top Si-containing layer adjacent to said device channel is thicker than the device channel.

8. The semiconductor structure of claim 7 further comprising an outer insulating spacer about the gate.

9. The semiconductor structure of claim 7 wherein said gate conductor comprises doped polysilicon.

10. The semiconductor structure of claim 6 wherein said some of said device channels are undoped or counter-doped.

11. The semiconductor structure of claim 10 wherein said top Si-containing layer under some of the MOSFET has a thickness which decreases with short channel lengths.

12. The semiconductor structure of claim 6 wherein some of device channels are doped.

13. The semiconductor structure of claim 14 wherein said top Si-containing layer under some of the MOSFET has a thickness that increases with short channel lengths.

14. The semiconductor structure of claim 6 wherein said device channels of some of said pluralarity of MOSFET are undoped or counterdoped and the device channel of the other MOSFETs are doped.