Microelectronic assemblies having compliant layers

• US 20060237836A1
• Filed: 06/23/2006
• Published: 10/26/2006
• Est. Priority Date: 10/31/1995
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Karavakis, Konstantine, Fjelstad, Joseph
• Granted Patent: US 7,872,344 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45155 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4951 : Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01009 : Fluorine [F]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A compliant semiconductor chip package assembly includes a a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Claims

1. A compliant semiconductor chip package assembly comprising:

a semiconductor chip having a plurality of chip contacts;

a compliant layer having a top surface, a bottom surface and sloping peripheral edges, wherein the bottom surface of the compliant layer overlies a surface of the semiconductor chip; and

a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, said traces extending along the sloping edges to the top surface of the compliant layer.

2. The assembly as claimed in claim 1, further comprising conductive terminals overlying said semiconductor chip, wherein said compliant layer supports said conductive terminals over said semiconductor chip.

3. The assembly as claimed in claim 2, wherein said conductive traces have first ends electrically connected with said contacts of said semiconductor chip and second ends electrically connected with said conductive terminals.

4. The assembly as claimed in claim 2, wherein said conductive terminals are movable relative to said semiconductor chip.

5. The assembly as claimed in claim 1, wherein said contacts are provided on a surface of said semiconductor chip.

6. The assembly as claimed in claim 5, wherein at least some of said contacts are provided in peripheral regions of said semiconductor chip.

7. The assembly as claimed in claim 5, wherein at least some of said contacts are provided in a central region of said semiconductor chip.

8. The assembly as claimed in claim 1, further comprising an encapsulant layer overlying top surfaces of said conductive traces.

9. The assembly as claimed in claim 8, wherein said encapsulant layer is selected from the group consisting of a curable liquid, silicone, flexibilized epoxy, thermoplastic and gel.

10. The assembly as claimed in claim 1, wherein said compliant layer is selected from the group consisting of silicone, flexibilized epoxy, a thermosetting epoxy, fluoropolymer, thermoplastic polymer and polyimide.

11. The assembly as claimed in claim 1, further comprising a dielectric cover layer over the top surface of said compliant layer and said conductive traces, wherein said dielectric cover layer has a plurality of apertures therein so that said terminals are accessible through the apertures.

12. The assembly as claimed in claim 1, wherein said sloping peripheral edges of said compliant layer extend in both vertical and horizontal directions.

13. The assembly as claimed in claim 12, wherein at least some of said sloping peripheral edges have first transition regions near the top surface of said compliant layer and second transition regions near the bottom surface of said compliant layer, and wherein both the first and second transition regions have respective radii of curvature.

14. A compliant semiconductor wafer assembly comprising:

a semiconductor wafer including a plurality of semiconductor chips, wherein each said semiconductor chip has a plurality of chip contacts;

a compliant layer having a top surface, a bottom surface and sloping peripheral edges, wherein the bottom surface of the compliant layer overlies a surface of said semiconductor wafer; and

a plurality of electrically conductive traces connected to said chip contacts of said semiconductor wafer, said traces extending along the sloping edges to the top surface of said compliant layer.

15. The assembly as claimed in claim 14, further comprising conductive terminals overlying said semiconductor wafer, wherein said compliant layer supports said conductive terminals over said semiconductor wafer.

16. The assembly as claimed in claim 15, wherein said conductive traces have first ends electrically connected with said contacts of said semiconductor wafer and second ends electrically connected with said conductive terminals.

17. The assembly as claimed in claim 15, wherein said conductive terminals are movable relative to said semiconductor wafer.

18. The assembly as claimed in claim 14, further comprising a dielectric cover layer over the top surface of said compliant layer and said conductive traces, wherein said dielectric cover layer has a plurality of apertures therein so that said terminals are accessible through the apertures.

19. The assembly as claimed in claim 14, wherein said sloping peripheral edges of said compliant layer extend in both vertical and horizontal directions.

20. The assembly as claimed in claim 14, wherein at least some of said sloping peripheral edges have first transition regions near the top surface of said compliant layer and second transition regions near the bottom surface of said compliant layer, and wherein both the first and second transition regions have respective radii of curvature.

21. A compliant microelectronic package comprising:

a microelectronic element having a first surface and a plurality of contacts accessible at the first surface;

a compliant layer having a top surface, a bottom surface and sloping edges, wherein the bottom surface of said compliant layer overlies the first surface of said microelectronic element;

a plurality of electrically conductive traces connected to said contacts of said microelectronic element, said conductive traces extending along said sloping edges to the top surface of said compliant layer; and

conductive terminals overlying said microelectronic element, said compliant layer supporting said conductive terminals over said microelectronic element for movement relative to said microelectronic element, wherein said conductive traces have first ends electrically connected with said contacts of said microelectronic element and second ends electrically connected with said conductive terminals.