NAND flash memory management

• US 20060239075A1
• Filed: 04/26/2005
• Published: 10/26/2006
• Est. Priority Date: 04/26/2005
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Love, Michael G., Singh, Harjit, Au, Stephen Z., Williams, Gregory G.
• Granted Patent: US 7,366,825 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A memory controller is utilized to overcome NAND flash memory'"'"'s propensity for comprising bad blocks of memory. The memory controller utilizes minimal hardware and is essentially transparent to a device requesting access to the NAND memory. A NAND flash memory device is configured to comprise a set of main blocks of memory and a set of auxiliary blocks of memory. Each block is divided into pages of memory and each page includes metadata. The metadata includes a block status indicator, indicating whether a block is good or bad. When receiving a request to access a page in the NAND flash memory, if the block in which the page resides is good, that block is accessed. If the block is bad, auxiliary memory is searched until a block containing the address of the bad block in its metadata is found. The found block is accessed in lieu of the bad block.

Claims

1. A method for accessing memory in a memory device, said method comprising:

configuring said memory device to comprise a main memory portion and an auxiliary memory portion, wherein;

each of said main memory portion and said auxiliary memory portion comprises a plurality of blocks of memory;

each block comprises a plurality of pages of memory; and

at least one page of each block comprises a status indicator stored therein indicative of a status of a block within which said at least one page is located;

receiving a request to access a page located in said main memory portion;

selecting a block from said main memory portion in which said requested page is located;

determining a status of said selected block to be one of good and bad in accordance a status indicator stored within a predetermined page of said selected block;

for a determined status of good, providing access to said requested page located in said selected block in said main memory portion;

for a determined status of bad, providing access to a corresponding page located in a designated block of said auxiliary memory portion in accordance with an address identifier stored within said predetermined page of said designated block, said address identifier being indicative of an address of said bad block.

2. A method in accordance claim 1, further comprising:

comparing an address identifier from said predetermined page of each block of said auxiliary memory portion to said address of said bad block until said designated block is found.

3. A method in accordance with claim 1, further comprising:

determining a status of a current page to be one of allocated and unallocated in accordance with a value of an address identifier of said current page.

4. A method in accordance with claim 1, wherein:

an address identifier comprising all binary 1s is indicative of an unallocated page; and

an address identifier comprising other than all binary 1s is indicative of an allocated page.

5. A method in accordance with claim 1, further comprising storing a value of an address of a bad block located in said main memory portion in an address identifier of a designated block located in said auxiliary memory portion.

6. A method in accordance with claim 1, wherein said memory device comprises a NAND flash memory device.

7. A method in accordance with claim 1, wherein said predetermined page comprises a 0^th page of a block.

8. A memory controller comprising:

a first input/output portion coupleable to a memory device;

a second input/output portion coupleable to an interfacing means; and

a memory management processor coupled to said first input/output portion and said second input/output portions, wherein upon receiving a request via said first input/output portion to access a page of memory of said memory device, said memory management processor;

selects a block from a main memory portion of said memory device in which said requested page is located;

determines a status of said selected block to be one of good and bad in accordance a status indicator stored within a predetermined page of said selected block;

for a determined status of good, provides access to said requested page located in said selected block in said main memory portion;

for a determined status of bad, provides access to a corresponding page located in a designated block of an auxiliary memory portion in accordance with an address identifier stored within said predetermined page of said designated block said address identifier being indicative of an address of said bad block.

9. A controller in accordance with claim 8, wherein:

said memory management processor compares an address identifier from said predetermined page of each block of said auxiliary memory portion to said address of said bad block until said designated block is found.

10. A controller in accordance with claim 8, wherein:

said memory management processor determines a status of a current page to be one of allocated and unallocated in accordance with an address identifier of said current page.

11. A controller in accordance with claim 10, wherein:

an address identifier comprising all binary 1s is indicative of an unallocated page; and

an address identifier comprising other than all binary 1s is indicative of an allocated page.

12. A controller in accordance with claim 10, wherein said memory management processor stores a value of an address of a bad block located in said main memory portion in an address identifier of a designated block located in said auxiliary memory portion.

13. A controller in accordance with claim 8, wherein said memory device comprises a NAND flash memory device.

14. A controller in accordance with claim 8, wherein said predetermined page comprises a 0^th page of a block.

15. A computer readable medium having stored thereon a data structure, said data structure comprising:

a main memory portion comprising a plurality of blocks of memory; and

an auxiliary memory portion comprising a plurality of blocks of memory, wherein;

each block of memory comprises a plurality of pages of memory;

at least one page of each block of memory comprises;

a payload portion for comprising payload data; and

a metadata portion for comprising metadata, said metadata portion comprising;

a first portion for comprising a value indicative of a status of a block within which said at least one page is located;

a second portion for comprising a value indicative of one of;

 

an address of a designated block located in said auxiliary memory portion; and

 

a status of a respective page.

16. A data structure in accordance with claim 15, wherein a status of a page comprises one of allocated and unallocated

17. A data structure in accordance with claim 15, wherein a status of a block comprises one of good and bad.

18. A data structure in accordance with claim 15, wherein:

a first portion comprising all binary 1s is indicative of an unallocated page; and

a first portion comprising other than all binary 1s is indicative of an allocated page.

19. A data structure in accordance with claim 15, wherein a predetermined page of each block comprises a value indicative of a status of a block.

20. A computer readable medium in accordance with claim 15, wherein said computer readable medium comprises a NAND flash memory device.