Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides

• US 20060244117A1
• Filed: 03/31/2006
• Published: 11/02/2006
• Est. Priority Date: 04/29/2005
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Karnezos, Marcos, Carson, Flynn
• Granted Patent: US 7,429,786 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Semiconductor package assemblies include a package subassembly, having at least one die affixed to, and electrically interconnected with, a die attach side of a first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the first package with the first side of the second substrate facing the die attach side of the first package substrate, and supported by a spacer or a spacer assembly. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. Also, methods for making such package assemblies include steps of providing a substrate, preferably as a strip of ball grid array (BGA) or land grid array (LGA) substrates; mounting die and interconnections onto the BGA or LGA substrate to form the package subassembly; mounting a spacer or spacer assembly upon the package subassembly; mounting a second substrate upon the adhesive on the spacer or upon the adhesive spacers; curing the adhesive or adhesive spacers; performing a plasma clean; wire bonding to form z-interconnection between the first side of the second substrate and the land side of the first package substrate; performing a plasma clean; performing a molding operation to enclose the first side of the substrate, the z-interconnection wire bonds and wire loops, the edges of the first package substrate, and the marginal area on the land side of the first package substrate, leaving exposed the second (“land”) side of the second substrate and an area of the land side of the first package substrate located within a marginal area; attaching second level interconnect solder balls to sites on the exposed area of the first package substrate; and (where the second substrate was provided in a strip or array) saw singulating to complete the package.

Claims

1. A semiconductor package assembly, comprising at least one die mounted upon and electrically connected to, a die attach side of a first package assembly substrate, and comprising a second substrate mounted over the first package die, the side of the first package substrate opposite the die attach side being a land side of the substrate, the second substrate having a first side facing the die attach side of the first package substrate, and a second side, being the land side, facing away from the die attach side of the first package substrate, so that the land sides of the substrates face away from one another, wherein z-interconnection of the first package substrate and the second substrate is by wire bonds connecting the first package assembly substrate and the second substrate, and wherein the package is encapsulated so that both at least a portion of the second substrate at one side of the package and at least a portion of the first package substrate at an opposite side of the assembly are exposed.

2. The assembly of claim 1 wherein the second substrate is larger than the first package substrate.

3. The assembly of claim 2 wherein the assembly encapsulation covers an area of the first side of the second substrate not contacted by the spacer or spacer structure, and encloses the z-interconnection wire bonds and wire loops, the edges of the first package, and the marginal area on the land side of the first package, so that both the land side of the second substrate and the area of the land side of the first substrate located within the marginal area, are left exposed.

4. The assembly of claim 1 wherein the first substrate is larger than the second package substrate,

5. The assembly of claim 3 wherein the assembly encapsulation covers an area of the first side of the second substrate not contacted by the spacer or spacer structure, and encloses the z-interconnection wire bonds and wire loops, the edges of the second package, and the marginal area on the land side of the second package, so that both the land side of the first substrate, and the area of the land side of the second substrate located within the marginal area, are left exposed.

6. The assembly of claim 1 wherein the first package assembly die is electrically connected with the first package substrate by wire bonds.

7. The assembly of claim 6 wherein the second substrate is supported over the first package die by a spacer, providing sufficient space between the first side of the substrate and the top of the die to accommodate a wire loop height.

8. The assembly of claim 6 wherein the second substrate is supported over the first package die by a spacer assembly, providing sufficient space between the first side of the substrate and the top of the die to accommodate a wire loop height.

9. The assembly of claim 6 wherein the second substrate is supported over the first package die by a spacer mounted upon the first package die.

10. The assembly of claim 6 wherein the second substrate is supported over the first package die by a spacer mounted upon the first package substrate.

11. The assembly of claim 1 wherein z-interconnection between the first package substrate and the second substrate is by wire bonds between wire bond sites in a marginal area on the land side of the first package substrate and peripherally located wire bond sites in a marginal area on the first side of the second substrate.

12. The assembly of claim 1 wherein z-interconnection between the first package substrate and the second substrate is by wire bonds between wire bond sites in a marginal area on the land side of the second package substrate and peripherally located wire bond sites in a marginal area on the first side of the first substrate.

13. The assembly of claim 1 wherein the first package die and the first package substrate, together with the electrical interconnection of the die with the substrate, constitute a package subassembly.

14. The assembly of claim 13 wherein the first package comprises a ball grid array substrate, and wherein second level interconnection of the package to underlying circuitry is made by interconnection at the exposed part of land side of the first package substrate.

15. The assembly of claim 13 wherein the first package comprises a ball grid array substrate, and wherein second level interconnection of the package to underlying circuitry is made by interconnection at the exposed land side of the second substrate.

16. The assembly of claim 13 wherein the first package assembly substrate is larger than the second substrate, and second level interconnection of the package to underlying circuitry is made by solder ball interconnection at the land side of the first assembly substrate.

17. A semiconductor package module, comprising an additional component mounted over the semiconductor package assembly of claim 1.

18. The semiconductor module of claim 17 wherein the additional component comprises at least one of:

a ball grid array (BGA) package;

or an additional LGA;

or a quad flat package (QFP);

or a quad flat nonleaded (QFN) package or lead frame chip scale package (LFCSP);

or a wire bonded die;

or a flip chip die;

or an optical sensor package;

or a micro-electro-mechanical sensor (MEMS) package;

or a passive device.

19. The semiconductor module of claim 17, further comprising a heat spreader mounted over the exposed land side of the second substrate.

22. A computer comprising the semiconductor package assembly of claim 1, electrically connected to underlying circuitry in the computer.

23. A portable computing device comprising the semiconductor package assembly of claim 1 electrically connected to underlying circuitry in the device.

24. A portable telecommunications device comprising the semiconductor package assembly of claim 1, electrically connected to underlying circuitry in the device.

20. A method for making a semiconductor package assembly, comprising:

providing a first substrate;

mounting die and electrical interconnections onto the substrate to form a package subassembly;

mounting an adhesive over the package subassembly;

mounting a second substrate upon the adhesive;

curing the adhesive;

performing a plasma clean;

wire bonding to form z-interconnection between the second substrate and the first substrate;

performing a plasma clean;

performing a molding operation, leaving exposed the second (“

land”

) side of the second substrate and an area of the land side of the first package substrate located within a marginal area.

21. A method for making a semiconductor package module, comprising making a semiconductor package assembly as recited in claim 20, and further comprising affixing and electrically connecting an additional component at an exposed substrate land side