Multi-rate, multi-port, gigabit serdes transceiver

• US 20060250985A1
• Filed: 03/27/2006
• Published: 11/09/2006
• Est. Priority Date: 10/29/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Baumer, Howard A.
• Granted Patent: US 7,355,987 B2
• Time in Patent Office: Days
• US Class Current: 370/258
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: Y04S 40/00 Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them

Abstract

A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port Serdes transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. The ring structure of the bus provides efficient communication between the logic core and the various data ports.

Claims

1-25. -25. (canceled)

26. A transceiver, comprising:

one or more parallel ports;

multiple serial ports; and

a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said one or more parallel ports and said multiple serial ports;

wherein said serial ports are each multi-rate ports capable of operating at one of 3.125 GHz, 2.5 GHz, and 1.25 GHz.

27. The transceiver of claim 26, wherein one of said serial ports operates according to a XAUI data protocol.

28. The transceiver of claim 26, wherein said serial ports convert between a XAUI serial protocol and a XGMII parallel protocol using a XGXS conversion protocol.

29. The transceiver of claim 26, wherein said serial ports operate according to a 10 Gigabit extension sub-letter (XGXS) protocol.

30. The transceiver of claim 26, wherein said one or more parallel ports operate at data rates of 1/10 of the data rates of said multiple serial ports.

31. The transceiver of claim 26, wherein said one or more parallel ports operate according to a XGMII parallel protocol.

32. The transceiver of claim 26, further comprising a packet bit error rate tester (BERT) connected to said bus, said packet BERT able to determine bit error rates of at least one of said one or more parallel ports and said multiple serial ports.

33. The transceiver of claim 26, wherein said multiple serial ports include four serial ports each configured to operate at 2.5 GHz so as to provide a combined 10 GHz serial rate for said transceiver.

34. The transceiver of claim 33, wherein said one or more parallel data ports are disabled.

35. The transceiver of claim 33, wherein said serial data ports operate according to a XAUI serial data protocol.

36. The transceiver of claim 26, wherein said multiple data ports include two serial ports and said one or more parallel ports include two parallel ports.

37. The transceiver of claim 26, wherein said two serial ports convert between a XAUI serial protocol and a XGMII parallel protocol using a XGXS conversion protocol, and said two parallel ports operate according to said XGMII data protocol.

38. The transceiver of claim 26, further including at least one management pad, said management pad able to determine data protocols and electricals for said transceiver.

39. The transceiver of claim 38, wherein said management pad is responsive to a data protocol of a first type of standard, and an electrical protocol of a second type of standard.

40. The transceiver of claim 39, wherein said first type of standard is one of an IEEE Std 802.3 clause 45 standard and an IEEE Std 802.3 clause 22 standard, and said second type of standard is the other of said IEEE Std 802.3 clause 45 standard and said IEEE Std 802.3 clause 22 standard.

41. A transceiver, comprising:

one or more parallel ports;

multiple serial ports;

a bus connecting said multiple parallel ports and said multiple serial ports on a common substrate with said multiple parallel ports and said one or more serial ports; and

a configuration block that enables and disables said one or more parallel ports and said multiple serial ports to configure said transceiver;

wherein said one or more parallel ports operate at data rates that are a fraction of the data rates of said multiple serial ports.

42. The transceiver of claim 41, wherein said serial data ports are each multi-rate ports capable of operating at one of 3.125 GHz, 2.5 GHz, and 1.25 GHz.