Host ethernet adapter for networking offload in server environment

• US 20060251120A1
• Filed: 04/01/2005
• Published: 11/09/2006
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Damon, Philippe, Vaidhyanathan, Natarajan, Calvignac, Jean Louis, Verplanken, Fabrice Jean, Basso, Claude, Verrilli, Colin Beaton, Fuhs, Ronald Edward, Sharma, Satya Prakash, Chang, Chih-Jen, Arimilli, Ravi Kumar, Willenborg, Scott Michael
• Granted Patent: US 7,586,936 B2
• Time in Patent Office: Days
• US Class Current: 370/469
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC

Abstract

An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.

Claims

1. An Ethernet adapter comprising:

a plurality of layers for allowing the adapter to receive and transmit packets from and to at least one processor;

wherein the plurality of layers include a demultiplexing mechanism to allow for partitioning of a plurality of resources of the at least one processor.

2. The Ethernet adapter of claim 1 wherein the demultiplexing mechanism allows for a direct path to a plurality of operating systems to be utilized concurrently within the processor.

3. The Ethernet adapter of claim 1 wherein the demultiplexing mechanism allows for a direct path to a plurality of applications to be utilized concurrently within the processor.

4. The Ethernet adapter of claim 1 wherein the demultiplexing mechanism allows for a direct path to a plurality of operating systems to be utilized concurrently within the processor and for a plurality of applications to be utilized concurrently within the processor.

5. The Ethernet adapter of claim 1 wherein the plurality of layers comprise:

a media access controller and serialization/deserialization (MAC and Serdes) layer;

a packet acceleration and virtualization layer for receiving packets from and providing packets to the MAC and Serdes layer; and

a host interface layer for communicating with the packet accelerator and virtualization layer and for interfacing with a private bus of the processor.

6. The Ethernet adapter of claim 1 wherein one logical switch is utilized for each physical port of the adapter.

7. The Ethernet adapter of claim 6 wherein one logical switch provides a plurality of logical ports wherein each of the plurality of logical ports supports a partition of the processor.

8. The Ethernet adapter of claim 5 wherein the MAC and Serdes layer comprises a receive Ethernet function for receiving packets;

and transmit Ethernet function for transmitting packets.

9. The Ethernet adapter of claim 5 wherein when appropriate a packet header is separated from the data payload to reduce the latency period for certain transactions.

10. A network interface controller (NIC) comprising:

an interface adapted to be coupled to a private bus of a processor; and

an Ethernet adapter, the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to at least;

wherein the plurality of layers include a demultiplexing mechanism to allow for partitioning of one processor a plurality of resources for the at least one processor.

11. The NIC of claim 10 wherein the demultiplexing mechanism allows for a direct path to a plurality of operating systems to be utilized concurrently within the processor.

12. The NIC of claim 10 wherein the demultiplexing mechanism allows for a direct path to a plurality of applications to be utilized concurrently within the processor.

13. The NIC of claim 10 wherein the demultiplexing mechanism allows for a direct path to a plurality of operating systems to be utilized concurrently within the processor and for a plurality of applications to be utilized concurrently within the processor.

14. The NIC of claim 10 wherein the plurality of layers comprise:

a media access controller and serialization/deserialization (MAC and Serdes) layer;

a packet acceleration and virtualization layer for receiving packets from and providing packets to the MAC and Serdes layer; and

a host interface layer for communicating with the packet accelerator and virtualization layer and for interfacing with a private bus of the processor.

15. The NIC of claim 10 wherein one logical switch is utilized for each physical port of the adapter.

16. The NIC of claim 15 wherein one logical switch provides a plurality of logical ports wherein each of the plurality of logical ports supports a partition of the processor.

17. The NIC of claim 14 wherein the MAC and Serdes layer comprises a receive Ethernet function for receiving packets;

and transmit Ethernet function for transmitting packets.

18. The NIC of claim 14 wherein when appropriate a packet header is separated from the data payload to reduce the latency period for certain transactions.

19. A server system comprising:

a server, the server including a processor and a memory coupled to the processor; and

a network interface controller (NIC) coupled to the processor via a private bus of the processor;

the NIC including an Ethernet adapter coupled to the private bus via a private bus interface, the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor;

wherein the plurality of layers include a demultiplexing mechanism to allow for partitioning of a plurality of resources for the at least one processor.

20. The server system of claim 19 wherein the demultiplexing mechanism allows for a direct path to a plurality of operating systems to be utilized concurrently within the processor.

21. The server system of claim 19 wherein the demultiplexing mechanism allows for a direct path to a plurality of applications to be utilized concurrently within the processor.

22. The server system of claim 19 wherein the demultiplexing mechanism allows for a direct path to a plurality of operating systems to be utilized concurrently within the processor and for a plurality of applications to be utilized concurrently within the processor.

23. The server system of claim 19 wherein the plurality of layers comprise:

a media access controller and serialization/deserialization (MAC and Serdes) layer;

a packet acceleration and virtualization layer for receiving packets from and providing packets to the MAC and Serdes layer; and

a host interface layer for communicating with the packet accelerator and virtualization layer and for interfacing with a private bus of the processor.

24. The server system of claim 19 wherein one logical switch is utilized for each physical port of the adapter.

25. The server system of claim 24 wherein one logical switch provides a plurality of logical ports wherein each of the plurality of logical ports supports a partition of the processor.

26. The server system of claim 23 wherein the MAC and Serdes layer comprises a receive Ethernet function for receiving packets;

and transmit Ethernet function for transmitting packets.

27. The Ethernet adapter of claim 23 wherein when appropriate a packet header is separated from the data payload to reduce the latency period for certain transactions.