Memory utilizing oxide-nitride nanolaminates
First Claim
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1. A method for operating a memory, comprising:
- writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes;
biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD;
grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed;
applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFET becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction;
reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes;
grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench;
precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD; and
applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell.
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Abstract
Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.
150 Citations
27 Claims
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1. A method for operating a memory, comprising:
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writing to one or more vertical MOSFETs arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array in a reverse direction, wherein each MOSFET in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator in the trenches, wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical MOSFETs and coupled to the source regions of each transistor along rows the vertical MOSFETs, wherein along columns of the vertical MOSFETs the source region of each column adjacent vertical MOSFET couple to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical MOSFETs in the reverse direction includes;
biasing a sourceline for two column adjacent vertical MOSFETs sharing a trench to a voltage higher than VDD;
grounding a bitline coupled to one of the drain regions of the two column adjacent vertical MOSFETs in the vertical MOSFET to be programmed;
applying a gate potential to the gate for each of the two column adjacent vertical MOSFETs to create a hot electron injection into the gate insulator of the vertical MOSFET to be programmed adjacent to the source region such that an addressed MOSFET becomes a programmed MOSFET and will operate at reduced drain source current in a forward direction;
reading one or more vertical MOSFETs in the DRAM array in a forward direction, wherein reading the one or more MOSFETs in the forward direction includes;
grounding a sourceline for two column adjacent vertical MOSFETs sharing a trench;
precharging the drain regions of the two column adjacent vertical MOSFETs sharing a trench to a fractional voltage of VDD; and
applying a gate potential of approximately 1.0 Volt to the gate for each of the two column adjacent vertical MOSFETs sharing a trench such that a conductivity state of an addressed vertical MOSFET can be compared to a conductivity state of a reference cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 12)
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8. A method of operating a memory array, comprising:
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writing a memory state to at least one of a plurality of vertical transistors in an array, including;
storing a charge within a storage layer of a nanolaminate insulator, wherein the storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;
wherein storing the charge is performed in a first direction; and
reading the memory state of the vertical transistor in a second direction opposite from the first direction. - View Dependent Claims (9, 10, 11)
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13. A method of operating a memory array, comprising:
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writing a memory state to at least one of a plurality of vertical transistors in an array, including;
storing a charge within a storage layer of a nanolaminate insulator, wherein the storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;
wherein storing the charge is performed in a first direction; and
reading the memory state of the vertical transistor in a second direction opposite from the first direction, including comparing a source/drain current of the vertical transistor in the second direction with source/drain current of a vertical reference transistor on an adjacent side of the trench. - View Dependent Claims (14, 15, 16, 17)
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18. A method of operating a memory array, comprising:
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writing a memory state to at least one of a plurality of vertical transistors in an array, including;
storing a charge within a nitride storage layer of a nanolaminate insulator, wherein the nitride storage layer is formed using atomic layer deposition techniques, and the nanolaminate insulator is located on a trench wall, and wherein the nanolaminate insulator layer separates a channel region within the trench wall from a gate located over the nanolaminate insulator within the trench;
wherein storing the charge is performed in a first direction; and
reading the memory state of the vertical transistor in a second direction opposite from the first direction. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification