Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method

• US 20060262631A1
• Filed: 11/12/2005
• Published: 11/23/2006
• Est. Priority Date: 11/12/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwak, Jin-Seok
• Granted Patent: US 7,289,385 B2
• Time in Patent Office: Days
• US Class Current: 365/230.30
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank selection signal control circuit includes a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect memory banks to a global data input/output line according to a predetermined sequence. For memory bank selected prior to a last selected memory bank in the predetermined sequence, the bank switch control unit outputs memory bank selection control signals that are enabled for a first time period P1, and for the last selected memory bank, the bank switch control unit outputs a memory bank selection control signal that is enabled for a second time period P2, wherein P2 is greater than P1. A switching unit sequentially connects each selected memory bank to the global data input/output line according to the predetermined sequence, and for a predetermined period P1 or P2, in response to the corresponding bank selection control signals.

Claims

1. A bank selection signal control circuit for a semiconductor memory device, the circuit comprising:

a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect memory banks to a global data input/output line according to a predetermined sequence,

wherein for each selected memory bank in the predetermined sequence which is selected prior to a last selected memory bank, the bank switch control unit outputs memory bank selection control signals that are enabled for a first time period P1, and

wherein for the last selected memory bank in the predetermined sequence, the bank switch control unit outputs a memory bank selection control signal that is enabled for a second time period P2, wherein P2 is greater than P1; and

a switching unit for sequentially connecting each selected memory bank to the global data input/output line according to the predetermined sequence, and for a predetermined period P1 or P2, in response to the corresponding bank selection control signals.

2. The circuit of claim 1, wherein the global data input/output line is connected to a data sense amplifier block for sensing and amplifying data transmitted through a local data bus of the selected memory bank.

3. The circuit of claim 2, wherein the data sense amplifier block comprises a current sense amplifier for sensing, amplifying and outputting data transmitted through the global data input/output line;

and

a voltage sense amplifier for sensing, amplifying and outputting an output of the current sense amplifier.

4. The circuit of claim 3, wherein the switching unit includes transistors that are respectively connected between the memory bank and the global data input/output line.

5. The circuit of claim 3, wherein the bank switch control unit comprises a plurality of unit control blocks, wherein each unit control block generates a memory bank selection control signal for a corresponding memory block, wherein each unit control block comprises:

a delay circuit for receiving the memory bank selection signal for the corresponding memory bank and delaying the bank selection signal for a predetermined period to generate a delayed bank selection signal;

a first logic circuit for receiving and logically combining the memory bank selection signals corresponding to other memory banks not including the memory bank selection signal applied to the delay circuit; and

a second logic circuit for receiving and logically combining output signals of the delay circuit and the first logic circuit to generate the bank selection control signal for the corresponding memory bank.

6. The circuit of claim 5, wherein the bank switch control unit comprises first, second, third and fourth unit control blocks which output respective first, second, third and fourth memory bank selection control signals for corresponding first, second, third and fourth memory blocks, in response to respective first, second, third and fourth memory bank selection signals individually input to the delay circuits of respective first, second, third and fourth unit control blocks, and wherein the first logic circuit for each unit control block receives as input the memory bank selection signals corresponding to all other memory banks.

7. The circuit of claim 5, wherein the first logic circuit is a NOR circuit.

8. The circuit of claim 7, wherein the second logic circuit is a NAND circuit.

9. A semiconductor memory device, comprising:

a plurality of memory banks;

a global data input/output line shared by the plurality of memory banks;

a data sense amplifier connected to the global data input/output line;

a multiplexer for selectively connecting the memory banks to the global data input/output line in response to bank selection control signals; and

a bank selection signal control circuit for generating the bank selection control signals to control the multiplexer, wherein at least one bank selection control signal for selectively connecting one of the memory banks with the global data input/output line is enabled for a time period P2 which is greater than a time period P1 for which all other bank selection control signals are enabled.

10. The device of claim 9, wherein the semiconductor memory device performs a bank interleave operation.

11. The device of claim 10, wherein the at least one bank selection control signal enabled for a time period of P2 is generated for a last selected memory bank of a predetermined sequence of selected memory banks in the bank interleave operation.

12. The device of claim 11, wherein the bank selection signal control circuit comprises:

a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect the memory banks to the global data input/output line according to the predetermined sequence; and

a multiplexer for sequentially connecting each selected memory bank to the global data input/output line according to the predetermined sequence, and for a predetermined period P1 or P2, in response to the corresponding bank selection control signals.

13. The device of claim 12, wherein the multiplexer includes transistors that are respectively connected between the memory bank and the global data input/output line.

14. The device of claim 12, wherein the bank switch control unit comprises a plurality of unit control blocks, wherein each unit control block generates a memory bank selection control signal for a corresponding memory block, wherein each unit control block comprises:

a delay circuit for receiving the memory bank selection signal for the corresponding memory bank and delaying the bank selection signal for a predetermined period to generate a delayed bank selection signal;

a first logic circuit for receiving and logically combining the memory bank selection signals corresponding to other memory banks not including the memory bank selection signal applied to the delay circuit; and

a second logic circuit for receiving and logically combining output signals of the delay circuit and the first logic circuit to generate the bank selection control signal for the corresponding memory bank.

15. The device of claim 14, wherein the bank switch control unit comprises first, second, third and fourth unit control blocks which output respective first, second, third and fourth memory bank selection control signals for corresponding first, second, third and fourth memory blocks, in response to respective first, second, third and fourth memory bank selection signals individually input to the delay circuits of respective first, second, third and fourth unit control blocks, and wherein the first logic circuit for each unit control block receives as input the memory bank selection signals corresponding to all other memory banks.

16. The device of claim 15, wherein the first logic circuit is a NOR circuit and the second logic circuit is a. NAND circuit.

17. A method for performing a bank interleaving operation in a semiconductor memory device having a plurality of memory banks, the method comprising:

receiving a sequence of bank selection signals for selecting a plurality of memory banks;

outputting a sequence of bank selection control signals in response to the sequence of bank selection signals to selectively connect the memory banks to a global data input/output line according to a predetermined sequence, wherein at least one of the bank selection control signals is enabled for a time period P2 which is greater than a time period P1 for which all other bank selection control signals are enabled.

18. The method of claim 17, wherein the at least one bank selection control signal enabled for the time period of P2 is output in response to the bank selection signal for a last selected memory bank in the predetermined sequence for the bank interleave operation.

19. The method of claim 18, wherein outputting the sequence of bank selection control signals in response to the sequence of bank selection signals, comprises:

delaying a selected one of the bank selection signals among the plurality of bank selection signals to generate a delayed bank selection signal;

logically combining one or more non-selected bank selection signals through a first logic circuit; and

logically combining the delayed bank selection signal and an output signal of the first logic circuit through a second logic circuit, to generate a bank selection control signal corresponding to the selected bank selection signal.

20. The method of claim 19, wherein the first logic circuit is a NOR circuit and the second logic circuit is a NAND circuit.